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ksz8462hl/ksz8462fhl ieee 1588 precision time protocol - enabled two - port 10/100mb/s ethernet switch with 8 or 16 bit host interface revision 1.0 ethersynch and linkmd are trademark s of micrel, inc . magic packet is a trademark of advanced micro devices, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com june 11, 2014 revision 1.0 general description the ksz8462 ethersynch ? product line consists of ieee 1588v2 - enabled ethernet switches, providing integrated communications and synchronization for a range of i ndustrial ethernet applications. the ksz8462 ethersynch product enables distributed, daisy?chained topologies preferred for industrial ethernet networks. conventional centralized (i.e., star?wired) topologies are also supported for dual?homed, fault tolera nt arrangements. a flexible 8 - or 16?bit general bus interface is provided for interfacing to an external host processor. the ksz8462 devices incorporate the ieee 1588v2 protocol. sub - microsecond synchronization is available via the use of hardware based t ime stamping and transparent clocks making it the ideal solution for time synchronized layer 2 communication in critical industrial applications. extensive general purpose i/o (gpio ) capabilities are available to use with the ieee 1588v2 ptp to efficientl y and accurately interface to locally - connected devices. complementing the i ndustry?s most - integrated ieee 1588v2 device is a precision timing protocol (ptp) v2 software stack that has been pre?qualified with the ksz84xx product family. the ptp stack has b een optimized around the ksz84xx chip architecture, and is available in source code format along with micrel?s chip driver. the wire?speed, store?and?forward switching fabric provides a full complement of quality - of - s ervice (qos) and congestion control fea tures optimized for real?time ethernet. ethersynch ? the ksz8462 product is built upon micrel?s industry ? leading ethernet technology, with features designed to offload host processing and streamline your overall design: ? wire?speed ethernet switching fabric with extensive filtering ? two integrated 10/100 base - tx phy t ransceivers , featuring the industry?s lowest power consumption ? full? featured qos support ? flexible management options that support common standard interfaces a robust assortment of power - management features including energy - e fficient ethernet (eee) have bee n designed in to satisfy energy - efficient environments. datasheets and support documentation are available on micrel?s web site at: www.micrel.com . ksz8462 top level architecture
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 2 revision 1.0 functional diagram ksz8462hl/ksz8462fhl functional diagram micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 3 revision 1.0 features management capabilities ? the ksz8462 includes all the functions of a 10/100 base ?t/tx/fx switch system which combines a switch engine, frame buffer management, address look - up table, queue management, mib counters, media access controllers (mac) and phy tran sceivers ? no n ? blocking store ? and ? forward switch fabric assures fast packet delivery by utilizing 1024 entry forwarding table ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port ? mib counters for fully - compliant statistics gathering ? 34 counters per port ? loopback modes for remote failure diagnostics ? rapid spanning tree protocol support (rstp) for topology management and ring/linear recovery robust phy ports ? two integrated ieee 802.3/802. 3u compliant ethernet transceivers supporting 10 base - t and 100 base - tx ? copper and 100 base - fx fiber mode support in the ksz8462fhl ? copper mode support in the ksz8462hl ? on?chip termination resistors and internal biasing for differential pairs to reduce power ? hp auto mdi/mdi?x crossover support eliminatin g the need to differentiate between straight or crossover cables in applications mac ports ? three internal media access control (mac) units ? 2kb yte jumbo packet support ? tail tagging mode (one byte added before fcs) s upport at port 3 to inform the processor which ingress port receives the packet and its priority ? programmable mac addresses for port 1 and port 2 and self ? address filtering support ? mac filtering functio n to filter or forward unknown u nicast packets ? port 1 and port 2 macs programmable as either end - to - end ( e2e ) or peer - to - peer ( p2p ) transparent clock (tc) ports for 1588 support advanced switch capabilities ? non ? blocking store ? and ? forward switch fabric assures fast packet delivery by utilizing 1024 entry forwarding table ? ieee 802.1q vlan for up to 16 groups with full range of vlan ids ? ieee 802.1p/q tag insertion or removal on a per port basis (egress) and support double ? tagging ? vlan id tag/untag options on per port basis ? fully compliant with ieee 802.3/802. 3 u standards ? ieee 802.3x full ? duplex wit h force mode option and half ? duplex backpressure collision flow control ? ieee 802.1 w rapid spanning tree protocol support ? igmp v1/v2/v3 snooping for multicast packet filtering ? qos/cos packets prioritization support: 802.1p, diffserv ? based and r e ? mapping of 802.1p priority field per port basis on four priority levels ipv4/ipv6 qos support ? ip v 6 m ulticast l istener d iscovery (mld) snooping support ? programmable rate limiting at the ingress and egress ports ? broadcast storm protection ? 1k entry forwarding table w ith 32k frame buffer ? 4 priority queues with dynamic packet mapping for ieee 802.1p, ipv4 tos (diffserv), ipv6 traffic class, etc. ? source address filtering for implementing ring topologies comprehensive configuration registers access ? complete register access via the parallel host i nterface ? facility to load mac address from eeprom at power - up and reset time ? i/o pin strapping facility to set certain register bits from i/o pins at reset time ? control registers configurable on ? the ? fly micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 4 revision 1.0 ieee 1588v2 ptp and clock synchronization ? fully compliant with the ieee 1588v2 precision time protocol ? one ? step or two ? step transparent c lock (tc) timing corrections ? e nd- to - end (e2e) or peer - to - peer ( p2p ) transparent clock ( tc ) ? grandmaster, m aster , s lave , and o rdin ary c lock (oc) s upport ? ieee1588v2 ptp m ulticast and u nicast frame support ? transports of ptp over ipv4/ipv6 udp and ieee 802.3 ethernet ? delay request ? response and peer delay mechanism ? ingress/e gress packet timestamp capture/recording and checksum u pd ate ? correction field u pd ate with residence time and link delay ? ieee1588v2 ptp packet filtering unit to reduce host processor overhead ? a 64 - bit adjustable system precision clock ? 12 trigger output u nits and 12 timestamp input units available for flexible ieee1588v2 control of 7 programmable gpio[6:0] pins synchronized to the precision time clock ? gpio pin usage for 1 pps generation, frequency generator, control bit streams, event monitoring, precision pulse generation, complex waveform generation host inter face ? selectable 8 - or 16 - bit wide interface ? supports b ig - and l ittle - endian processors ? indirect data bus for data, address and byte enable to access any i/o registers and rx/tx fifo buffers ? large internal memory with 12kbyte for rx fifo and 6kbytes for tx fifo ? programmable low, high and overrun water mark for flow control in rx fifo ? efficient architecture design with configurable host interrupt schemes to minimize host cpu overhead and utilization ? queue management unit (qmu) supervises data transfers across this interface power and power management ? single 3.3v power supply with optional vdd i/o for 1.8v, 2.5v or 3.3v ? i ntegrated low voltage ( ~1.3v ) low - noise regulator (ldo) output for digital and analog core power. ? supports ieee p802.3az energy - efficient et hernet ( eee ) to reduce power consumption in transceivers in lpi state ? full?chip hardware or software power down (all registers value are not saved and strap ? in value will re ? strap after release the power down) ? energy d etect p ower d own (ed pd ), which disables the phy transceiver when cables are removed ? wake - on- lan supported with configurable packet control ? dynamic clock tree control to reduce clocking in areas not in use ? power consumption less than 0.5w additional features ? single 25mhz 50 ppm reference clock requirement ? comprehensive programmable two led indicators support for link, activity, full/half duplex and 10/100 speed ? led pins directly controllable ? industrial temperature r ange: ? 40 o c to +85 o c ? 64- pin, 10mm 10mm, lead free, rohs, lqfp package ? 0 .11 m technology for lower power consumption applications ? industrial ethernet appl ications that employ ieee 802.3 - compliant macs. (ethernet/ip, profinet, modbus tcp, etc) ? real?time ethernet networks requiring sub?microsecond synchronization over standard e thernet ? iec 61850 networks supporting power substation automation ? networked measurement and control systems ? industrial automation and motion control systems ? test and measurement equipment micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 5 revision 1.0 ordering information part number temperature range package lead finish description ksz8462hli ? 40 c to +85 c 64?pin lqfp pb?free industrial temperature device with generic host interface ksz8462f h li ? 40 c to +85 c 64?pin lqfp pb?free industrial temperature device with generic host interface and fiber (100 base- fx) support ksz8462hli -eval evaluation board with ksz8462hli . also supports the ksz8462fhli. revision history revision date summary of changes 1.0 6/ 11 /14 initial release of ksz8462hl/fhl product datasheet. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 6 revision 1.0 contents general description ................................................................................................................................................................ 1 functional diagram ................................................................................................................................................................. 2 features .................................................................................................................................................................................. 3 management capabilit ies .................................................................................................................................................... 3 robust phy ports ............................................................................................................................................................... 3 mac ports ........................................................................................................................................................................... 3 advanced switch capa bilities ............................................................................................................................................. 3 ipv4/ipv6 qos support ........................................................................................................................................................ 3 comprehensive configuration registers access ................................................................................................................ 3 ieee 1588v2 ptp and clock synchronization .................................................................................................................... 4 host interface ...................................................................................................................................................................... 4 power and power management .......................................................................................................................................... 4 additional features .............................................................................................................................................................. 4 applications ............................................................................................................................................................................. 4 ordering information ............................................................................................................................................................... 5 revision history ...................................................................................................................................................................... 5 contents .................................................................................................................................................................................. 6 acronyms .............................................................................................................................................................................. 20 pin configuration ................................................................................................................................................................... 23 pin descri ption ...................................................................................................................................................................... 24 strapping options ................................................................................................................................................................. 29 functional description ........................................................................................................................................................... 30 direction terminology ........................................................................................................................................................... 30 physical (phy) block ............................................................................................................................................................ 31 100base? tx transmit ..................................................................................................................................................... 31 100base?tx receive ...................................................................................................................................................... 31 scrambler/de?scrambler (100base?tx only) ................................................................................................................ 31 pll clock synthesizer (recovery) .................................................................................................................................... 31 100base?fx operation ................................................................................................................................................... 31 100base?fx signal detection ......................................................................................................................................... 32 100base?fx far?end fault ............................................................................................................................................ 32 10base?t transmit .......................................................................................................................................................... 32 10base?t r eceive ........................................................................................................................................................... 32 mdi/mdi?x auto crossover .............................................................................................................................................. 32 straight cable ................................................................................................................................................................ 33 crossover cable ............................................................................................................................................................ 33 auto?negotiation ............................................................................................................................................................... 34 linkmd ? cabl e diagnostics ............................................................................................................................................... 35 access ............................................................................................................................................................................ 35 usage ............................................................................................................................................................................. 35 on?chip termination resistors ........................................................................................................................................ 35 loopback support ............................................................................................................................................................. 35 far?end loopback ......................................................................................................................................................... 36 near?end (remote) loopback ...................................................................................................................................... 36 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 7 revision 1.0 media access controller (mac) block .................................................................................................................................. 37 mac operation .................................................................................................................................................................. 37 address lookup ................................................................................................................................................................. 37 learning ............................................................................................................................................................................. 37 migration ............................................................................................................................................................................ 37 aging .................................................................................................................................................................................. 37 forwarding ......................................................................................................................................................................... 37 inter packet gap (ipg) ...................................................................................................................................................... 40 back?off algorithm ............................................................................................................................................................ 40 late collision ..................................................................................................................................................................... 40 legal packet size .............................................................................................................................................................. 40 flow control ....................................................................................................................................................................... 40 half?duplex backpressure ................................................................................................................................................ 40 broadcast storm protection ............................................................................................................................................... 41 port individual mac address and source port filtering ................................................................................................... 41 address filtering function ................................................................................................................................................. 41 switch block .......................................................................................................................................................................... 43 switching engine ............................................................................................................................................................... 43 spanning tre e support ..................................................................................................................................................... 43 rapid spanning tree support ........................................................................................................................................... 44 discarding state ............................................................................................................................................................. 44 learning state ................................................................................................................................................................ 44 forwarding sta te ............................................................................................................................................................ 44 tail tagging mode ............................................................................................................................................................. 44 igmp support .................................................................................................................................................................... 45 ?igmp? snooping ........................................................................................................................................................... 45 ?multicast address insertion? in the static mac table .................................................................................................. 45 ipv6 mld snooping ....................................................................................................................................................... 45 port mirroring support ....................................................................................................................................................... 46 ?receive only? mirror - on- a - port .................................................................................................................................... 46 ?transmit only? mirror - on- a - port ................................................................................................................................... 46 ?receive and transmit? mirror - on- two - ports ................................................................................................................ 46 ieee 802.1q vlan support .............................................................................................................................................. 46 qos priority support .......................................................................................................................................................... 47 port?based priority ............................................................................................................................................................ 47 802.1p?based priority ....................................................................................................................................................... 47 802.1p priority field re?mapping ..................................................................................................................................... 48 diffserv - based priority ...................................................................................................................................................... 48 rate - limiting support ........................................................................................................................................................ 49 mac address filtering function ........................................................................................................................................ 49 queue management unit (qmu) .......................................................................................................................................... 50 transmit queue (txq) frame format .............................................................................................................................. 50 frame transmitting path operation in txq ...................................................................................................................... 51 driver routine for transmitting packets from host processor to ksz8462 ..................................................................... 52 receive queue (rxq) frame format ............................................................................................................................... 53 frame receiving path operation in rxq ......................................................................................................................... 53 driver routine for receiving packets from the ksz8462 to the host processor ............................................................. 54 ieee 1588 precision time protocol (ptp) block .................................................................................................................. 56 ieee 1588 ptp clock types ............................................................................................................................................. 57 ie ee 1588 ptp one?step or two?step clock operation ............................................................................................... 57 ieee 1588 ptp best master clock selection ................................................................................................................... 57 ieee 1588 ptp system time clock ................................................................................................................................. 57 updating the system time clock .................................................................................................................................... 59 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 8 revision 1.0 ieee 1588 ptp message processing ............................................................................................................................... 60 ieee 1588 ptp ingress packet processing .................................................................................................................. 60 ieee 1588 ptp egress packet processing ................................................................................................................... 60 ieee 1588 ptp event triggering and timestamping ....................................................................................................... 61 ieee 1588 ptp trigger outputs ....................................................................................................................................... 61 ieee 1588 ptp event timestamp input ........................................................................................................................... 61 ieee 1588 ptp event interrupts ....................................................................................................................................... 62 ieee 1588 gpio ............................................................................................................................................................... 62 general purpose and ieee 1588 input/output (gpio) ........................................................................................................ 63 overview ............................................................................................................................................................................ 63 gpio pin functionality control .......................................................................................................................................... 63 gpio pin control register layout ..................................................................................................................................... 64 gpio trigger output units and timestamp input unit interrupts ..................................................................................... 67 using the gpio pins with the trigger output units .......................................................................................................... 68 creating a low?going pulse at a specific time ........................................................................................................... 68 creating a high?going pulse at a specific time .......................................................................................................... 68 creating a free running clock source ......................................................................................................................... 69 creating finite length periodic bit streams at a specific time .................................................................................... 70 creating finite length non?uniform bit streams at a specific time ............................................................................ 70 creating complex waveforms at a specific time ......................................................................................................... 71 using the gpio pins with the timestamp input units ....................................................................................................... 72 timestamp value ........................................................................................................................................................... 72 timestamping an incoming low?going edge ............................................................................................................... 72 timestamping an incoming high?going edge .............................................................................................................. 73 device clocks ........................................................................................................................................................................ 74 gpio and ieee 1588 related clocking ............................................................................................................................ 74 power .................................................................................................................................................................................... 75 power management .............................................................................................................................................................. 77 normal operation mode .................................................................................................................................................... 77 energy detect mode .......................................................................................................................................................... 77 global soft power - down mode ......................................................................................................................................... 78 energy - efficient ethernet (eee) ........................................................................................................................................ 78 transmit direction control for mii mode ........................................................................................................................ 79 receive direction control for mii mode ......................................................................................................................... 79 wake - on - lan ................................................................................................................................................................... 80 detection of ene rgy ........................................................................................................................................................... 80 detection of linkup ............................................................................................................................................................ 80 wake?up packet ............................................................................................................................................................... 80 magic packet? ................................................................................................................................................................. 80 interrupt generation on power management related events .......................................................................................... 81 to generate an interrupt on the pme signal pin .......................................................................................................... 81 to generate an interrupt on the intrn signal pin ....................................................................................................... 81 interfaces ............................................................................................................................................................................... 82 bus interface unit (biu) / host interface ........................................................................................................................... 82 supported transfers ...................................................................................................................................................... 82 physical data bus size .................................................................................................................................................. 82 little and big endian support ........................................................................................................................................ 83 asynchronous interface ................................................................................................................................................. 83 biu summary ................................................................................................................................................................. 84 serial eeprom interface .................................................................................................................................................. 85 device registers ................................................................................................................................................................... 86 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 9 revision 1.0 register map of cpu accessible i/o registers .................................................................................................................... 88 i/o registers ...................................................................................................................................................................... 88 internal i/o r egister space mapping for switch control and configuration (0x000 ? 0x0ff) ...................................... 88 internal i/o register space mapping for host interfa ce unit (0x100 ? 0x16f) ............................................................. 94 internal i/o register space mapping for the qmu (0x170 ? 0x1ff) ............................................................................ 96 internal i/o register space mapping for ptp trigger output (12 units, 0x200 ? 0x3ff) ............................................ 98 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 ? 0x5ff) ............................ 107 internal i/o register space mapping for ptp 1588 clock and global control (0x600 ? 0x7ff) ............................... 119 register bit d efinitions ........................................................................................................................................................ 122 internal i/o register mapping for switch control and configuration (0x000 ? 0x0ff) ................................................... 122 chip id and enable register (0x00 ? 0x001): cider ..................................................................................................... 122 switch global control register 1 (0x002 ? 0x003): sgcr1 ........................................................................................... 122 switch global control register 2 (0x004 ? 0x00 5): sgcr2 ........................................................................................... 124 switch global control register 3 (0x006 ? 0x007): sgcr3 ........................................................................................... 125 0x008 ? 0x00b: reserved ............................................................................................................................................... 125 swit ch global control register 6 (0x00c ? 0x00d): sgcr6 .......................................................................................... 126 switch global control register 7 (0x00e ? 0x00f): sgcr7 .......................................................................................... 127 mac address register 1 (0x010 ? 0x011): macar1 ..................................................................................................... 128 mac address register 2 (0x012 ? 0x013): macar2 ..................................................................................................... 128 mac address register 3 (0x014 ? 0x015): macar3 ..................................................................................................... 128 type - of - service (tos) priority control registers ............................................................................................................... 129 tos priority control register 1 (0x016 ? 0x017): tosr1 .............................................................................................. 129 tos priority control register 2 (0x018 ? 0x019): tosr2 .............................................................................................. 130 tos priority control register 3 (0x01a ? 0x01b): tosr3 ............................................................................................. 131 tos priority control register 4 (0x01c ? 0x1d): tosr4 .............................................................................................. 131 tos priority control register 5 (0x01e ? 0x1 f): tosr5 ............................................................................................... 132 tos priority control register 6 (0x020 ? 0x021): tosr6 .............................................................................................. 133 tos priority control register 7 (0x022 ? 0x023): tosr7 .............................................................................................. 133 tos priority control register 8 (0x024 ? 0x025): tosr8 .............................................................................................. 134 indirect access data registers ........................................................................................................................................... 135 indirect access data register 1 (0x026 ? 0x027): iadr1 .............................................................................................. 135 indirect access data register 2 (0x028 ? 0x029): iadr2 .............................................................................................. 135 indirect access data register 3 (0x02a ? 0x02b): iadr3 ............................................................................................. 135 indirect access data register 4 (0x02c ? 0x02d): iadr4 ............................................................................................. 135 indirect access data register 5 (0x02e ? 0 x02f): iadr5 .............................................................................................. 136 indirect access control register (0x030 ? 0x031): iacr ............................................................................................... 136 power management control and wake - up event status ................................................................................................... 137 power management control and wake?up event status (0x032 ? 0x033): pmctrl .................................................. 137 power management event enable register (0x034 ? 0x035): pmee ............................................................................ 138 go sleep time and clock tree power - down control registers ........................................................................................ 139 go sleep time register (0x036 ? 0x037): gst .............................................................................................................. 139 clock tree power - down control register (0x038 ? 0x039): ctpdc ............................................................................. 139 0x03a ? 0x04b: reserved ............................................................................................................................................... 139 phy and mii basic control registers ................................................................................................................................. 140 phy 1 and mii basic control register (0x04c ? 0x04d): p1mbcr ............................................................................... 140 phy 1 and mii basic status register (0x04e ? 0x04f): p1mbsr ................................................................................. 141 phy 1 phyid low register (0x050 ? 0x051): phy1ilr ................................................................................................ 142 phy 1 phyid high register (0x052 ? 0x053): p hy1ihr .............................................................................................. 142 phy 1 auto?negotiation advertisement register (0x054 ? 0x055): p1anar ............................................................... 143 phy 1 auto?negotiation link partner ability register (0x056 ? 0x057): p1anlpr ...................................................... 144 phy 2 and mii basic control register (0x058 ? 0x059): p2mbcr ................................................................................ 144 phy 2 and mii basic status register (0x05a ? 0x05b): p2mbsr ................................................................................. 146 phy 2 phyid low register (0x05c ? 0x05d): phy2ilr ............................................................................................... 147 phy 2 phyid high register (0x05e ? 0x05f): phy2ihr .............................................................................................. 147 phy 2 auto?negotiation advertisement register (0x060 ? 0x061): p2anar ............................................................... 147 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 10 revision 1.0 phy 2 auto?negotiation link partner ability register (0x062 ? 0x063): p2anlpr ...................................................... 148 0x0x06 4 ? 0x065: reserved ............................................................................................................................................ 148 phy1 special control and status register (0x066 ? 0x067): p1phyctrl .................................................................. 149 0x068 ? 0x069: reserved ................................................................................................................................................ 149 phy 2 special control and status register (0x06a ? 0x06b): p2phyctrl ................................................................. 149 port 1 control registers ...................................................................................................................................................... 150 port 1 control register 1 (0x06c ? 0x06d): p1cr1 ....................................................................................................... 150 port 1 control register 2 (0x06e ? 0x06f): p1cr2 ........................................................................................................ 152 port 1 vid control register (0x070 ? 0x071): p1vidcr ................................................................................................ 153 port 1 control register 3 (0x072 ? 0x073): p1cr3 ........................................................................................................ 153 port 1 ingress rate control register 0 (0x074 ? 0x 075): p1ircr0 ............................................................................... 154 port 1 ingress rate control register 1 (0x076 ? 0x077): p1ircr1 ............................................................................... 155 port 1 egress rate control register 0 (0x078 ? 0x079): p1ercr0 .............................................................................. 155 port 1 egress rate control register 1 (0x07a ? 0x07b): p1ercr1 ............................................................................. 155 port 1 phy special control/status, linkmd (0x07c ? 0x07d): p1scslmd .................................................................. 156 port 1 control registe r 4 (0x07e ? 0x07f): p1cr4 ........................................................................................................ 157 port 1 status register (0x080 ? 0x081): p1sr ............................................................................................................... 158 0x082 ? 0x083: reserved ................................................................................................................................................ 159 port 2 control registers ...................................................................................................................................................... 160 po rt 2 control register 1 (0x084 ? 0x085): p2cr1 ........................................................................................................ 160 port 2 control register 2 (0x086 ? 0x087): p2cr2 ........................................................................................................ 162 port 2 vid control register (0x088 ? 0x089): p2vidcr ................................................................................................ 163 port 2 control register 3 (0x08a ? 0x08b): p2cr3 ....................................................................................................... 163 port 2 ingress rate control register 0 (0x08c ? 0x08d): p2ircr0 .............................................................................. 164 port 2 ingress rate control register 1 (0x08e ? 0x08f): p2ircr1 .............................................................................. 164 port 2 egress rate control register 0 (0x090 ? 0x091): p2ercr0 .............................................................................. 165 port 2 egress rate control register 1 (0x092 ? 0x093): p2ercr1 .............................................................................. 165 port 2 phy special control/status, linkmd (0x094 ? 0x095): p2scslmd ................................................................... 166 port 2 control registe r 4 (0x096 ? 0x097): p2cr4 ........................................................................................................ 167 port 2 status register (0x098 ? 0x099): p2sr ............................................................................................................... 169 0x09a ? 0x09b: reserved ............................................................................................................................................... 170 port 3 control registers ...................................................................................................................................................... 171 port 3 control register 1 (0x09c ? 0x09d): p3cr1 ....................................................................................................... 171 port 3 control register 2 (0x09e ? 0x09f): p3cr2 ........................................................................................................ 172 port 3 vid control register (0x0a0 ? 0x0a1): p3vidcr ............................................................................................... 173 port 3 control register 3 (0x0a2 ? 0x0a3): p3cr3 ....................................................................................................... 174 port 3 ingress rate control register 0 (0x0a4 ? 0x 0a5): p3ircr0 .............................................................................. 174 port 3 ingress rate control register 1 (0x0a6 ? 0x0a7): p3ircr1 .............................................................................. 175 port 3 egress rate control register 0 (0x0a8 ? 0x0a9): p3ercr0 ............................................................................. 175 port 3 egress rate control register 1 (0x0aa ? 0x0ab): p3ercr1 ............................................................................. 175 switch global control regi sters ......................................................................................................................................... 176 switch global control register 8 (0x0ac ? 0x0ad): sgcr8 ......................................................................................... 176 switch global control register 9 (0x0ae ? 0x0af): sgcr9 ......................................................................................... 177 source address filtering registers .................................................................................................................................... 178 source address filtering mac address 1 register low (0x0b0 ? 0x0b1): safmaca1l ............................................. 178 source address filtering mac address 1 register middle (0x0b2 ? 0x0b3): safmaca1m ........................................ 178 source address filtering mac address 1 register high (0x0b4 ? 0x0b5): safmaca1h ............................................ 178 source address filtering mac address 2 register low (0x0b6 ? 0x0b7): safmaca2l ............................................. 178 source address filtering mac address 2 register middle (0x0b8 ? 0x0b9): safmaca2m ........................................ 178 source address filtering mac address 2 register high (0x0ba ? 0x0bb): safmaca2h ........................................... 179 0x0bc ? 0x0c7: reserved .............................................................................................................................................. 179 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 11 revision 1.0 txq rate control registers ............................................................................................................................................... 180 port 1 txq rate control register 1 (0x0c8 ? 0x0c9): p1txqrcr1 ............................................................................ 180 port 1 txq rate control register 2 (0x0ca ? 0x0cb): p1txqrcr2 ........................................................................... 180 port 2 txq rate control regist er 1 (0x0cc ? 0x0cd): p2txqrcr1 ........................................................................... 181 port 2 txq rate control register 2 (0x0ce ? 0x0cf): p2txqrcr2 ........................................................................... 181 port 3 txq rate control register 1 (0x0d0 ? 0x0d1): p3txqrcr1 ............................................................................ 182 port 3 txq rate control register 2 (0x0d2 ? 0x0d3): p3txqrcr2 ............................................................................ 182 0x0d4 ? 0x0d5: reserved .............................................................................................................................................. 182 input and output multiplex selection registers .................................................................................................................. 183 input and output multiplex selection register (0x0d6 ? 0x0d7): iomxsel .................................................................. 183 configuration status and serial bus mode registers ......................................................................................................... 184 configuration status and seria l bus mode register (0x0d8 ? 0x0d9): cfgr .............................................................. 184 0x0da ? 0x0db: reserved .............................................................................................................................................. 184 auto - negotiation next page registers ............................................................................................................................... 185 port 1 auto?negotiation next page transmit register (0x0dc ? 0x0dd): p1anpt ..................................................... 185 port 1 auto?negotiation link partner received next page register (0x0de ? 0x0df): p1alprnp ........................... 186 eee and link partner advertisement registers ................................................................................................................. 187 port 1 eee and link partner advertisement register (0x0e0 ? 0x0e1): p1eeea ......................................................... 187 port 1 eee wake error count register (0x0e2 ? 0x0e3): p1eeewec ........................................................................ 188 port 1 eee control/status and auto?negotiation expansion register (0x0e4 ? 0x0e5): p1eeecs ............................ 188 port 1 lpi recovery time counter register (0x0e6): p1lpirtc .................................................................................. 190 buffer load to l pi control 1 register (0x0e7): bl2lpic1 ............................................................................................. 190 port 2 auto?negotiation next page transmit register (0x0e8 ? 0x0e9): p2anpt ....................................................... 190 port 2 auto?negotiation link partner received next page register (0x0ea ? 0x0eb): p2alprnp ........................... 191 port 2 eee and link partner advertisement register (0x0ec ? 0x0ed): p2eeea ....................................................... 192 port 2 eee wake error count register (0x0ee ? 0x0ef): p2eeewec ........................................................................ 193 port 2 eee control/status and auto?negotiation expansion register (0x0f0 ? 0x0f1): p2eeecs ............................ 193 port 2 lpi recovery time counter register (0x0 f2): p2lpirtc .................................................................................. 195 pcs eee control register (0x0f3): pcseeec ............................................................................................................. 195 empty txq to lpi wait time control register (0x0f4 ? 0x0f5): etlwtc ................................................................... 195 buffer load to lpi control 2 register (0x0f6 ? 0x0f7): bl2lpic2 ............................................................................... 196 0x0f8 ? 0x0ff: reserved ............................................................................................................................................... 196 internal i/o register space mapping for interrupts, biu, and global reset (0x100 ? 0x1ff) ........................................... 197 0x100 ? 0x107: reserved ................................................................................................................................................ 197 chip configuration register (0x108 ? 0x1 09): ccr ....................................................................................................... 197 0x10a ? 0x10f: reserved ............................................................................................................................................... 197 host mac address registers: marl, marm and marh .............................................................................................. 198 host mac address register low (0x110 ? 0x111): marl ............................................................................................. 198 host mac address register middle (0x112 ? 0x113): marm ........................................................................................ 198 host mac address register high (0x114 ? 0x115): marh ........................................................................................... 198 0x116 ? 0x121: reserved ................................................................................................................................................ 198 eepr om control register (0x122 ? 0x123): eepcr .................................................................................................... 199 memory bist info register (0x124 ? 0x125): mbir ....................................................................................................... 199 global reset register (0x126 ? 0x127): grr ................................................................................................................ 200 0x128 ? 0x129: reserved ................................................................................................................................................ 200 wake - up frame control register (0x12a ? 0x12b): wfcr .......................................................................................... 201 0x12c ? 0x12f: reserved ............................................................................................................................................... 201 wake - up frame 0 crc0 register (0x130 ? 0x131): wf0crc0 ................................................................................... 201 wake - up frame 0 crc1 register (0x132 ? 0x133): wf0crc1 ................................................................................... 202 wake - up frame 0 byte mask 0 register (0x134 ? 0x135): wf0bm0 ............................................................................ 202 wake - up frame 0 byte mask 1 register (0x136 ? 0x137): wf0bm1 ............................................................................ 202 wake - up frame 0 byte mask 2 register (0x138 ? 0x139): wf0bm2 ............................................................................ 202 wake - up frame 0 byte mask 3 register (0x13a ? 0x13b): wf0bm3 ........................................................................... 202 0x13c ? 0x13f: reserved ............................................................................................................................................... 203 wake - up frame 1 crc0 register (0x140 ? 0x141): wf1crc0 ................................................................................... 203 wake - up frame 1 crc1 register (0x142 ? 0x143): wf1crc1 ................................................................................... 203 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 12 revision 1.0 wake - up fr ame 1 byte mask 0 register (0x144 ? 0x145): wf1bm0 ............................................................................ 203 wake - up frame 1 byte mask 1 register (0x146 ? 0x147): wf1bm1 ............................................................................ 203 wake - up frame 1 byte mask 2 register (0x148 ? 0x149): wf1bm2 ............................................................................ 204 wake - up frame 1 byte mask 3 register (0x14a ? 0x14b): wf1bm3 ........................................................................... 204 0x14c ? 0x14f: reserved ............................................................................................................................................... 204 wake - up frame 2 crc0 register (0x150 ? 0x151): wf2crc0 ................................................................................... 204 wake - up frame 2 crc1 register (0x152 ? 0x153): wf2crc1 ................................................................................... 204 wake - up frame 2 byte mask 0 register (0x154 ? 0x155): wf2bm0 ............................................................................ 205 wake - up frame 2 byte mask 1 register (0x156 ? 0x157): wf2bm1 ............................................................................ 205 wake - up frame 2 byte mask 2 re gister (0x158 ? 0x159): wf2bm2 ............................................................................ 205 wake - up frame 2 byte mask 3 register (0x15a ? 0x15b): wf2bm3 ........................................................................... 205 0x15c ? 0x15f: reserved ............................................................................................................................................... 205 wake - up frame 3 crc0 register (0x160 ? 0x161): wf3crc0 ................................................................................... 206 wake - up frame 3 crc1 register (0x162 ? 0x163): wf3crc1 ................................................................................... 206 wake - up frame 3 byte mask 0 register (0x164 ? 0x165): wf3bm0 ............................................................................ 206 wake - up frame 3 byte mask 1 register (0x166 ? 0x167): wf3bm1 ............................................................................ 206 wake - up frame 3 byte mask 2 register (0x168 ? 0x169): wf3bm2 ............................................................................ 206 wake - up frame 3 byte mask 3 register (0x16a ? 0x16b): wf3bm3 ........................................................................... 207 0x16c ? 0x16f: reserved ............................................................................................................................................... 207 internal i/o register space mapping for the queue management unit (qmu) (0x170 ? 0x1ff) ...................................... 208 transmit control register (0x170 ? 0x171): txcr ......................................................................................................... 208 transmit status register (0x172 ? 0x173): txsr .......................................................................................................... 209 receive control register 1 (0x174 ? 0x175): rxcr1 .................................................................................................... 209 receive control register 2 (0x176 ? 0x177): rxcr2 .................................................................................................... 210 txq memory information register (0x178 ? 0x179): txmir ......................................................................................... 211 0x17a ? 0x17b: reserved ............................................................................................................................................... 211 receive frame header status register (0x17c ? 0x17d): rxfhsr ............................................................................ 211 receive frame header byte count register (0x17e ? 0x17f): rxfhbcr ................................................................... 212 txq command register (0x180 ? 0x181): txqcr ....................................................................................................... 213 rxq command register (0x182 ? 0x183): rxqcr ....................................................................................................... 213 tx frame data pointer register (0x184 ? 0x185): txfdpr ......................................................................................... 214 rx frame data pointer register (0x186 ? 0x187): rxfdpr ......................................................................................... 215 0x188 ? 0x18b: reserved ............................................................................................................................................... 215 rx duration timer threshold register (0x18c ? 0x18d): rxdttr .............................................................................. 215 rx data byte count threshold register (0x18e ? 0x18f): rxdbctr ......................................................................... 216 internal i/o register space mapping for interrupt registers (0x190 ? 0x193) ................................................................... 217 interrupt enable register (0x190 ? 0x191): ier ............................................................................................................. 217 interrupt status register (0x192 ? 0x193): isr .............................................................................................................. 218 0x194 ? 0x19b: reserved ............................................................................................................................................... 219 inte rnal i/o register space mapping for the queue management unit (qmu) (0x19c ? 0x1b9) ..................................... 220 rx frame count and threshold register (0x1 9c ? 0x19d): rxfctr .......................................................................... 220 tx next total frames size register (0x19e ? 0x19f): txntfsr ................................................................................ 220 mac address hash table register 0 (0x1a0 ? 0x1a1): mahtr0 ................................................................................. 220 multicast table register 0 ........................................................................................................................................... 220 mac address hash table register 1 (0x1a2 ? 0x1a3): mahtr1 ................................................................................. 221 multicast table register 1 ........................................................................................................................................... 221 mac address hash table register 2 (0x1a4 ? 0x1a5): mahtr2 ................................................................................. 221 multicast table register 2 ........................................................................................................................................... 221 mac address hash table register 3 (0x1a6 ? 0x1a7): mahtr3 ................................................................................. 221 multicast table register 3 ........................................................................................................................................... 221 0x1a8 ? 0x1af: reserved ............................................................................................................................................... 221 flow control low water mark register (0x1b0 ? 0x1b1): fclwr ................................................................................ 221 flow control high water mark register (0x1b2 ? 0x1b3): fchwr .............................................................................. 222 flow control overrun water mark register (0x1b4 ? 0x1b5): fcowr ........................................................................ 222 rx frame count register (0x1b8 ? 0x1b9): rxfc ....................................................................................................... 222 0x1ba ? 0x1ff: reserved .............................................................................................................................................. 2 22 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 13 revision 1.0 inte rnal i/o register space mapping for trigger output units (12 units, 0x200 ? 0x3ff) ................................................ 223 trigger error register (0x200 ? 0x201): tr ig_err ...................................................................................................... 223 trigger active register (0x202 ? 0x203): trig_active ............................................................................................... 223 trigger done register (0x204 ? 0x205): trig_done ................................................................................................... 223 trigger enable register (0x206 ? 0x207): trig_en ...................................................................................................... 224 trigger software reset register (0x208 ? 0x209): trig_sw_rst .............................................................................. 224 trigger output unit 12 output pps pulse wi dth register (0x20a ? 0x20b): trig12_pps_width ............................ 224 0x20c ? 0x21f: reserved ............................................................................................................................................... 224 trigger output unit 1 target time in nanoseconds low?word register (0x220 ? 0x221): trig1_tgt_nsl ............ 225 trigger output unit 1 target time in nanoseconds high?word register (0x222 ? 0x223): trig1_tgt_nsh ........... 225 trigger output unit 1 target time in seconds low?word register (0x224 ? 0x225): trig1_tgt_sl ....................... 225 trigger output unit 1 target time in seconds high?word register (0x226 ? 0x227): trig1_tgt_sh ...................... 225 trigger output unit 1 configuration and control register 1 (0x228 ? 0x229): trig1_cfg_1 ...................................... 226 trigger output unit 1 configuration and control register 2 (0x22a ? 0x22b): trig1_cfg_2 ..................................... 228 trigger output unit 1 configuration and control register 3 (0x22c ? 0x22d): trig1_cfg_3 .................................... 228 trigger output unit 1 configuration and control register 4 (0x22e ? 0x22f): trig1_cfg_4 ..................................... 228 trigger output unit 1 configuration and control register 5 (0x230 ? 0x231): trig1_cfg_5 ...................................... 228 trigger output unit 1 configuration and control register 6 (0x232 ? 0x233): trig1_cfg_6 ...................................... 229 trigger output unit 1 configuration and control register 7 (0x234 ? 0x235): trig1_cfg_7 ...................................... 229 trigger output unit 1 configuration and control register 8 (0x236 ? 0x237): trig1_cfg_8 ...................................... 229 0x238 ? 0x23f: reserved ............................................................................................................................................... 229 trigger output unit 2 target time and output configuration/control registers (0x240 ? 0x257) ................................. 230 trigger output unit 2 configuration and control register 1 (0x248 ? 0x249): trig2_cfg_1 .................................. 230 0x258 ? 0x25f: reserved ............................................................................................................................................... 230 trigger ou tput unit 3 target time and output configuration/control registers (0x260 ? 0x277) ................................. 230 0x278 ? 0x27f: reserved ............................................................................................................................................... 230 trigger output unit 4 target time and output configuration/control registers (0x280 ? 0x297) ................................. 230 0x298 ? 0x29f: reserved ............................................................................................................................................... 230 trig ger output unit 5 target time and output configuration/control registers (0x2a0 ? 0x2b7) ................................ 230 0x2b8 ? 0x2bf: reserved ............................................................................................................................................... 230 trigger output unit 6 target time and output configuration/control registers (0x2c0 ? 0x2d7) ................................ 230 0x2d8 ? 0x2df: reserved .............................................................................................................................................. 230 trig ger output unit 7 target time and output configuration/control registers (0x2e0 ? 0x2f7) ................................ 231 0x2f8 ? 0x2ff: reserved ............................................................................................................................................... 231 trigger output unit 8 target time and output configuration/control registers (0x300 ? 0x317) ................................. 231 0x318 ? 0x31f: reserved ............................................................................................................................................... 231 trig ger output unit 9 target time and output configuration/control registers (0x320 ? 0x337) ................................. 231 0x338 ? 0x33f: reserved ............................................................................................................................................... 231 trigger output unit 10 target time and output configuration/control registers (0x340 ? 0x357) ............................... 231 0x358 ? 0x35f: reserved ............................................................................................................................................... 231 trigger output unit 11 target time and output configuration/control registers (0x360 ? 0x377) ............................... 231 0x378 ? 0x37f: reserved ............................................................................................................................................... 231 trigger output unit 12 target time a nd output configuration/control registers (0x380 ? 0x397) ............................... 231 0x398 ? 0x3ff: reserved ............................................................................................................................................... 231 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 14 revision 1.0 internal i/o register space mapping for ptp timestamp inputs (12 units, 0x400 ? 0x5ff) ............................................ 232 timestamp ready register (0x400 ? 0x401): ts_rdy ................................................................................................. 232 timestamp enable register (0x402 ? 0x403): ts_en ................................................................................................... 232 timestamp software reset register (0x404 ? 0x405): ts_sw_rst ............................................................................ 232 0x406 ? 0x41f: reserved ............................................................................................................................................... 232 ti mestamp unit 1 status register (0x420 ? 0x421): ts1_status ............................................................................... 233 timestamp unit 1 configuration and control register (0x422 ? 0x423 ): ts1_cfg ...................................................... 233 timestamp unit 1 input 1st sample time in nanoseconds low?word register (0x424 ? 0x425): ts1_smpl1_nsl ........................................................................................................................................................ 234 timestamp unit 1 input 1st sample time in nanoseconds high?word register (0x426 ? 0x427): ts1_smpl1_nsh ........................................................................................................................................................ 234 timestamp unit 1 input 1st sample time in seconds low?word register (0x428 ? 0x429): ts1_smpl1_sl ........................................................................................................................................................... 234 timestamp unit 1 input 1st sample time in seconds high?word register (0x42a ? 0x42b): ts1_smpl1_sh .......................................................................................................................................................... 234 timestamp unit 1 input 1st sample time in sub?nanoseconds register (0x42c ? 0x42d): ts1_smpl1_sub_ns ................................................................................................................................................. 235 0x42e ? 0x433: reserved ............................................................................................................................................... 235 time stamp unit 1 input 2nd sample time in nanoseconds low?word register (0x434 ? 0x435): ts1_smpl2_nsl ........................................................................................................................................................ 235 timestamp unit 1 input 2nd sample time in nanoseconds high?word register (0x436 ? 0x437): ts1_smpl2_nsh ........................................................................................................................................................ 235 timestamp unit 1 input 2nd sample time in seconds low?word register (0x438 ? 0x439): ts1_smpl2_sl ........................................................................................................................................................... 235 timestamp unit 1 input 2nd sample time in seconds high?word register (0x43a ? 0x43b): ts1_smpl2_sh .......................................................................................................................................................... 236 timestamp unit 1 input 2nd sample time in sub?nanoseconds register (0x43c ? 0x43d): ts1_smpl2_sub_ns ................................................................................................................................................. 236 0x43e ? 0x43f: reserved ............................................................................................................................................... 236 timestamp unit 2 status/configuration/control and input 1st sample tim e registers (0x440 ? 0x44d) ...................... 236 0x44e ? 0x453: reserved ............................................................................................................................................... 236 timestamp unit 2 input 2nd sample time registers (0x454 ? 0x45d) .......................................................................... 236 0x45e ? 0x45f: reserved ............................................................................................................................................... 236 timestamp unit 3 status/configuration/control and input 1st sample time registers (0x460 ? 0x46d) ...................... 236 0x46e ? 0x473: reserved ............................................................................................................................................... 236 timestamp unit 3 input 2nd sample time registers (0x474 ? 0x47d) .......................................................................... 237 0x47e ? 0x47f: reserved ............................................................................................................................................... 237 timestamp unit 4 status/configuration/control and input 1st sample time registers (0x480 ? 0x48d) ...................... 237 0x48e ? 0x493: reserved ............................................................................................................................................... 237 time stamp unit 4 input 2nd sample time registers (0x494 ? 0x49d) .......................................................................... 237 0x49e ? 0x49f: reserved ............................................................................................................................................... 237 timestamp unit 5 status/configuration/control and input 1st sample time registers (0x4a0 ? 0x4ad) ..................... 237 0x4ae ? 0x4b3: reserved .............................................................................................................................................. 237 timestamp unit 5 input 2nd sample time registers (0x4b4 ? 0x4bd) ......................................................................... 237 0x4be ? 0x4bf: reserved .............................................................................................................................................. 237 timestamp unit 6 status/configuration/control and input 1st samp le time registers (0x4c0 ? 0x4cd) .................... 237 0x4ce ? 0x4d3: reserved .............................................................................................................................................. 237 timestamp unit 6 input 2nd sample time registers (0x4d4 ? 0x4dd) ......................................................................... 238 0x4de ? 0x4df: reserved .............................................................................................................................................. 238 timestamp unit 7 status/configuration/control and input 1st samp le time registers (0x4e0 ? 0x4ed) ..................... 238 0x4ee ? 0x4f3: reserved ............................................................................................................................................... 238 timestamp unit 7 input 2nd sample time registers (0x4f4 ? 0x4fd) .......................................................................... 238 0x4fe ? 0x4ff: reserved ............................................................................................................................................... 238 timestamp unit 8 status/configuration/control and input 1st samp le time registers (0x500 ? 0x50d) ...................... 238 0x50e ? 0x513: reserved ............................................................................................................................................... 238 timestamp unit 8 input 2nd sample time registers (0x514 ? 0x51d) .......................................................................... 238 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 15 revision 1.0 0x51e ? 0x51f: reserved ............................................................................................................................................... 238 time stamp unit 9 status/configuration/control and input 1st sample time registers (0x520 ? 0x52d) ...................... 238 0x52e ? 0x533: reserved ............................................................................................................................................... 238 timestamp unit 9 input 2nd sample time registers (0x534 ? 0x53d) .......................................................................... 239 0x53e ? 0x53f: reserved ............................................................................................................................................... 239 time stamp unit 10 status/configuration/control and input 1st sample time registers (0x540 ? 0x54d) .................... 239 0x54e ? 0x553: reserved ............................................................................................................................................... 239 timestamp unit 10 input 2nd sample time registers (0x554 ? 0x55d) ........................................................................ 239 0x55e ? 0x55f: reserved ............................................................................................................................................... 239 timestamp unit 11 status/configuration/control and input 1st sample time registers (0x560 ? 0x56d) .................... 239 0x56e ? 0x573: reserved ............................................................................................................................................... 239 timestamp unit 11 input 2nd sa mple time registers (0x574 ? 0x57d) ........................................................................ 239 0x57e ? 0x57f: reserved ............................................................................................................................................... 239 timestamp unit 12 status/configuration/control and input 1st sample time registers (0x580 ? 0x58d) .................... 239 0x58e ? 0x593: reserved ............................................................................................................................................... 239 timestamp unit 12 input 2nd sample time registers (0x594 ? 0x59d) ........................................................................ 240 0x59e ? 0x5a3: reserved ............................................................................................................................................... 240 timestamp unit 12 input 3rd sample time registers (0x5a4 ? 0x5ad) ........................................................................ 240 0x5ae ? 0x5b3: reserved .............................................................................................................................................. 240 time stamp unit 12 input 4th sample time registers (0x5b4 ? 0x5bd) ........................................................................ 240 0x5be ? 0x5c3: reserved .............................................................................................................................................. 240 timestamp unit 12 input 5th sample time registers (0x5c4 ? 0x5cd) ........................................................................ 240 0x5ce ? 0x5d3: reserved .............................................................................................................................................. 240 time stamp unit 12 input 6th sample time registers (0x5d4 ? 0x5dd) ........................................................................ 240 0x5de ? 0x5e3: reserved .............................................................................................................................................. 240 timestamp unit 12 input 7th sample time registers (0x5e4 ? 0x5ed) ........................................................................ 240 0x5ee ? 0x5f3: reserved ............................................................................................................................................... 240 timestamp unit 12 input 8th sample time registers (0x5f4 ? 0x5fd) ......................................................................... 241 0x5fe ? 0x5ff: reserved ............................................................................................................................................... 241 internal i/o register space mapping for ptp 1588 clock and global control (0x600 ? 0x7ff) ....................................... 242 ptp clock control register (0x600 ? 0x601): ptp_clk_ctl ...................................................................................... 242 0x602 ? 0x603: reserved ................................................................................................................................................ 242 ptp real time clock in nanoseconds low?word register (0x604 ? 0x605): ptp_rtc_nsl .................................... 243 ptp real time clock in nanoseconds high?word register (0x606 ? 0x607): ptp_rtc_nsh .................................. 243 ptp real time clock in seconds low?word register (0x608 ? 0x609): ptp_rtc_sl .............................................. 243 ptp real time clock in seconds high?word register (0x60a ? 0x60b): ptp_rtc_sh ............................................ 243 ptp real time clock in phase register (0x60c ? 0x60d): ptp_rtc_phase ........................................................... 244 0x60e ? 0x60f: reserved ............................................................................................................................................... 244 ptp rate in sub?nanoseconds low?word register (0x610 ? 0x611): ptp_sns_rate_l ....................................... 244 ptp rate in sub?nanoseconds high?word and control register (0x612 ? 0x613): ptp_sns_rate_h ..................................................................................................................................................... 245 ptp temporary adjustment mo de duration in low?word register (0x614 ? 0x615): ptp_temp_adj_dura_l .......................................................................................................................................... 245 ptp temporary adjustment mode duration in high?word register (0x616 ? 0x617): ptp_temp_adj_dura_h ......................................................................................................................................... 245 0x618 ? 0x61f: reserved ............................................................................................................................................... 245 ptp message configuration 1 register (0x620 ? 0x621): ptp_msg_cfg_1 .............................................................. 246 ptp message configuration 2 register (0x622 ? 0x623): ptp_msg_ cfg_2 .............................................................. 247 ptp domain and version register (0x624 ? 0x625): ptp_domain_ver ................................................................... 248 0x626 ? 0x63f: reserved ............................................................................................................................................... 248 ptp port 1 receive latency register (0x640 ? 0x641): ptp_p1_rx_latency ........................................................ 248 ptp port 1 transmit latency register (0x642 ? 0x643): ptp_ p1_tx_latency ........................................................ 249 ptp port 1 asymmetry correction register (0x644 ? 0x645): ptp_p1_asym_cor ................................................... 249 ptp port 1 link delay register (0x646 ? 0x647): ptp_p1_link_dly ......................................................................... 249 ptp port 1 egress timestamp low?word register for pdelay_req and delay_req (0x648 ? 0x649): p1_xdly_req_tsl ................................................................................................................................................... 249 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 16 revision 1.0 ptp port 1 egress timestamp high?word register for pdelay_req and delay_req (0x64a ? 0x64b): p1_xdly_req_tsh ................................................................................................................................................... 250 ptp port 1 egress timestamp low?word register for sync (0x64c ? 0x64d): p1_sync_tsl ................................. 250 ptp port 1 egress timestamp high?word register for sync (0x64e ? 0x64f): p1_sync_tsh ................................ 250 ptp port 1 egress timestamp low?word register for pdelay_resp (0x650 ? 0x651): p1_pdly_resp_tsl .......... 250 ptp port 1 egress timestamp high?word register for pdelay_resp (0x652 ? 0x653): p1_pdly_resp_tsh ........ 250 0x654 ? 0x65f: reserved ............................................................................................................................................... 251 ptp port 2 receive latency register (0x660 ? 0x661): ptp_p2_rx_latency ........................................................ 251 ptp port 2 transmit latency register (0x662 ? 0x663): ptp_p2_tx_latency ........................................................ 251 ptp port 2 asymmetry correction register (0x664 ? 0x665): ptp_p2_asym_cor ................................................... 251 ptp port 2 link delay register (0x666 ? 0x667): ptp_p2_link_dly ......................................................................... 251 ptp port 2 egress timestamp low?word register for pdelay_req and delay _req (0x668 ? 0x669): p2_xdly_req_tsl ................................................................................................................................................... 251 ptp port 2 egress timestamp high?word register for pdelay_req and delay_req (0x66a ? 0x66b): p2_xdly_req_tsh ................................................................................................................................................... 252 ptp port 2 egress timestamp low?word register for sync (0x66c ? 0x66d): p2_sync_tsl ................................. 252 ptp port 2 egress timestamp high?word register for sync (0x66e ? 0x66f): p2_sync_tsh ................................ 252 ptp port 2 egress timestamp low?word register for pdelay_resp (0x670 ? 0x671): p2_pdly_resp_tsl .......... 252 ptp port 2 egress timestamp high?word register for pdelay_resp (0x672 ? 0x673): p2_pdly_resp_tsh ........ 252 0x674 ? 0x67f: reserved ............................................................................................................................................... 253 gpio monitor register (0x680 ? 0 x681): gpio_monitor ........................................................................................... 253 gpio output enable register (0x682 ? 0x683): gpio_oen ......................................................................................... 253 0x684 ? 0x687: reserved ................................................................................................................................................ 253 ptp trigger unit interrupt status register (0x688 ? 0x689): ptp_trig_is ................................................................. 253 ptp trigger unit interrupt enable register (0x68a ? 0x68b): ptp_trig_ie ............................................................... 253 ptp timest amp unit interrupt status register (0x68c ? 0x68d): ptp_ts_is .............................................................. 254 ptp timestamp unit interrupt enable register (0x68e ? 0x68f): ptp_ts_ie ............................................................. 254 0x690 ? 0x733: reserved ................................................................................................................................................ 255 dsp control 1 register (0x734 ? 0x735): dsp_cntrl_6 ............................................................................................ 255 0x736 ? 0x747: reserved ................................................................................................................................................ 255 analog control 1 register (0x748 ? 0x749): ana_cntrl_1 ......................................................................................... 255 analog control 3 register (0x74c ? 0x74d): ana_cntrl_3 ....................................................................................... 256 0x74e ? 0x7ff: reserved ............................................................................................................................................... 256 mana gement information base (mib) counters ................................................................................................................. 257 mib counter examples: ................................................................................................................................................... 259 additional mib information .............................................................................................................................................. 259 static mac address table .................................................................................................................................................. 260 st atic mac table lookup examples: .............................................................................................................................. 261 dynamic mac address table ............................................................................................................................................. 262 dynamic mac address lookup example: ...................................................................................................................... 262 vlan table ......................................................................................................................................................................... 263 vlan table looku p examples: ....................................................................................................................................... 263 absolute maximum ratings ................................................................................................................................................ 264 operating ratings ............................................................................................................................................................... 264 electrical characteristics ..................................................................................................................................................... 264 timing specifications .......................................................................................................................................................... 268 host interface read / write timing ................................................................................................................................. 268 auto?negotiation timing ................................................................................................................................................. 269 trigger output unit and timestamp input unit timing .................................................................................................... 270 serial eeprom interface timing .................................................................................................................................... 272 reset timing and power sequencing ................................................................................................................................. 273 reset circuit guidelines ...................................................................................................................................................... 274 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 17 revision 1.0 reference circuits ? led strap - in pins .............................................................................................................................. 275 reference clock ? connection and selection .................................................................................................................... 276 selection of reference crystal ............................................................................................................................................ 276 selection of isolation transformers ..................................................................................................................................... 277 package information and recommended landing pattern ................................................................................................ 278 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 18 revision 1.0 list of figures figure 1. typical straight cable connection ........................................................................................................................ 33 figure 2. typical crossover cable connection .................................................................................................................... 33 figure 3. auto negotiation and parallel operation ............................................................................................................... 34 figure 4. near - end and far - end loopback .......................................................................................................................... 36 figure 5. destination address lookup flow chart in stage one ......................................................................................... 38 figure 6. destination address resolution flow chart in stage two .................................................................................... 39 figure 7. tail tag frame format .......................................................................................................................................... 44 figure 8. 802.1p priority field format .................................................................................................................................. 48 figure 9. host tx single frame in manual enqueue flow diagram .................................................................................... 52 figure 10. host rx single or multiple frames in auto - dequeue flow diagram .................................................................. 55 figure 11. ptp system clock overview ............................................................................................................................... 58 figure 12. trigger output unit organization and associated registers ............................................................................... 65 figure 13. timestamp input unit organization and a ssociated registers ........................................................................... 66 figure 14. trigger unit interrupts .......................................................................................................................................... 67 figure 15. timestamp input unit interrupts .......................................................................................................................... 67 figure 16. complex waveform generation using cascade mode ....................................................................................... 71 figure 17. recommended low - voltage power connection using an external low - voltage - regulator .............................. 75 figu re 18. recommended low - voltage power connections using the internal low - voltage regulator ............................ 76 figure 19. traffic activity and eee ....................................................................................................................................... 78 figure 20. ksz8462 8 - bit and 16 - bit data bus connections ............................................................................................... 84 figure 21. interface and register mapping ........................................................................................................................... 86 figure 22. host interfac e read/write timing ...................................................................................................................... 268 figure 23. auto - negotiation timing .................................................................................................................................... 269 figure 24. trigger output unit and timestamp input unit timing ...................................................................................... 270 figure 25. serial eeprom timing ..................................................................................................................................... 272 figure 26. ksz8462 reset and power sequence timing .................................................................................................. 273 figure 27. sample reset circuit ......................................................................................................................................... 274 figure 28. recommended reset circuit for interfacing with a cpu/fpga reset output ................................................. 274 figure 29. typical led strap - in circuit .............................................................................................................................. 275 figure 30. 25mhz crystal and oscillator clock connection options ................................................................................. 276 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 19 revision 1.0 list of tables table 1. mdi/mdi - x pin definitions ...................................................................................................................................... 32 table 2. mac address filtering scheme .............................................................................................................................. 42 table 3. spanning tree states ............................................................................................................................................. 43 table 4. tail tag rules ......................................................................................................................................................... 45 tabl e 5. fid + da lookup in vlan mode ............................................................................................................................ 46 table 6. fid + sa lookup in vlan mode ............................................................................................................................ 47 table 7. frame format for transmit queue ......................................................................................................................... 50 table 8. transmit control word bit fields ............................................................................................................................ 50 table 9. transmit byte count format ................................................................................................................................... 51 table 10. register setting for transmit function block ....................................................................................................... 51 table 11. frame format for receive queue ........................................................................................................................ 53 table 12. register settings for receive function block ....................................................................................................... 54 table 13. ksz8462 gpio pin resources ............................................................................................................................. 63 table 14. trigger output units and timestamp input units summary ................................................................................. 64 table 15. gpio pin control register layout ........................................................................................................................ 64 table 16. ksz8462 device clocks ....................................................................................................................................... 74 table 17. voltage options and requirements ...................................................................................................................... 75 table 18. power management and internal blocks .............................................................................................................. 77 table 19. available interfaces ............................................................................................................................................... 82 table 20. bus interface unit signal grouping ....................................................................................................................... 83 table 21. ksz8462 serial eeprom format ........................................................................................................................ 85 table 22. mapping of functional areas within the address space ...................................................................................... 87 table 23. ingress or egress data rate limits .................................................................................................................... 154 table 24. format of per - port mib counters ....................................................................................................................... 257 table 25. port 1 mib counters ? indirect memory offset ................................................................................................... 258 table 26. "all ports dropped packet" mib counter format ............................................................................................... 259 table 27. "all ports dropped packet" mib counters? indirect memory offsets ................................................................. 259 table 28. static mac table format (8 entries) .................................................................................................................. 260 table 29. dynamic mac address table format (1024 entries) ......................................................................................... 262 table 30. vlan table format (16 entries) ......................................................................................................................... 263 table 31. host interface read/write timing parameters ................................................................................................... 268 table 32. auto - negotiation timing parameters .................................................................................................................. 269 table 33. trigger output unit and timestamp input unit timing parameters ................................................................... 271 table 34. serial eeprom timing parameters ................................................................................................................... 272 table 35. reset timing parameters ................................................................................................................................... 273 table 36. typical reference crystal characteristics .......................................................................................................... 276 table 37. transformer selection criteria ............................................................................................................................ 277 table 38. qualified single port magnetic ............................................................................................................................ 277 micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 20 revision 1.0 acronyms biu bus interface u nit the host interface function that performs code conversion , buffering, and the like required for communications to and from a network . bpdu bridge protocol data unit a packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination. cmos complementary metal oxide semiconductor a common semiconductor manufacturing technique in which positive and negative types of transistors ar e combined to form a current gate that in turn forms an effective means of controlling electrical current through a chip. crc cyclic redundancy check a common technique for detecting data transmiss ion errors. crc for ethernet is 32 bits long. cut - through switch a switch typically processes received packets by reading in the full packet (storing), then processing the packet to determine where it needs to go, then forwarding it. a cut?through switch simply reads in the first bit of an incoming packet and forwards the packet. cut?through switches do not store the packet. da destination address the address to send packets. dma direct memory access a design in which memory on a chip is controlled inde pendently of the cpu. emi electromagnetic interference a naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. in computer tec hnology, computer devices are susceptible to emi because electromagnetic fields are a byproduct of passing electricity through a wire. data lines that have not been properly shielded are susceptible to data corruption by emi. fcs frame check sequence see crc. fid frame or filter id specifies the frame identifier. alternately is the filter identifier. gpio general purpose input/output general purpose input/output pins are signal pins that can be controlled or monitored by hardware and software to perform specific tasks. igmp internet group management protocol the protocol defined by rfc 1112 for ip multicast transmissions. ipg inter - packet gap a time delay between successive data packets mandated by the network standard for protocol reasons. in ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. ipg is used to correct timing differences between a transmitter and receiver. during the ipg, no data is transferred, and information in the gap can be discarded or additions inserted without impact on data integrity. isi inter - symbol interference the disruption of transmitted code caused by adjacent pulses affecting or interfering with each other. isa industry standard architecture a bus architecture used in the ibm pc/xt and pc/at . jumbo packet a packet larger than the standard ethernet packet (1500 bytes). large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 21 revision 1.0 acronyms (continued) mac media access controller a functional block responsible for implementing the media access control layer which is a sub layer of the data link layer . mdi medium dependent interface an ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null?modem, or crossover, cable. mdi provides the standard interface to a particular media (copper or fiber) and is therefor e ?media dependent?. mdi -x medium dependent interface crossover an ethernet port connection that allows networked end stations (i.e., pcs or workstations) to connect to each other using a null?modem, or crossover, cable. for 10/100 full?duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver. when connecting two computers together, a cable that crosses the tx and rx is required to do this. with auto mdi?x, the phy senses the corre ct tx and rx roles, eliminating any cable confusion. mib management information base the mib comprises the management portion of network devices. this can include things like monitoring traffic levels and faults (statistical), and can also change operatin g parameters in network nodes (static forwarding addresses). mii media independent interface the mii accesses phy registers as defined in the ieee 802.3 specification. nic network interface card an expansion board inserted into a computer to allow it to be connected to a network. most nics are designed for a particular type of network, protocol, and media, although some can serve multiple networks. npvid non - port vlan id the port vlan id value is used as a vlan reference. nrz non - return to zero a type of signal data encoding whereby the signal does not return to a zero state in between bits. phy a device or functional block which performs the physical layer interface function in a network. pll phase - locked loop an electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. a pll ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a signal and divide a frequency. ptp precision time protocol a protocol, ieee 1588 as applied to this device, for synchronizing the clocks of devices attached to a specific network. qmu queue management unit manages packet traffic between the port 3 internal mac and the system host (processor) interface . the qmu has built?in packet memories for receive and transmit functions called txq (transmit queue) and rxq (receive queue). for the qmu, ?transmit? means into port 3 of the switch from the external host, and ?receive? is from the switch to the external host. this terminology is the opposite of the terminology used for other ksz8462 switch blocks. sa source address the address from which information has been sent. tsu timestamp input unit the functional block which captures signals on the gpio pins and assigns a time to the specific event. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 22 revision 1.0 acronyms (continued) tdr time domain reflectometry tdr is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. they send a signal down the conductor and measure the time it takes for the whole or part of the signal to return. tsu timestamp input unit the functional block which captures signals on the gpio pins and assigns a time to the specific event. utp unshielded twisted pair commonly a cable containing 4 twisted pairs of wires. the wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. vlan virtual local area network a confi guration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 23 revision 1.0 pin configuration 64- pin lqfp micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 24 revision 1.0 pin description pin number pin name type pin function 1 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (? differential). 2 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential). 3 agnd gnd analog ground. 4 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (? differential). 5 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential). 6 vdd_al p this pin is used as an input for the low - voltage analog power. its source should have appropriate filtering with a ferrite bead and capacitors. 7 iset o current set : sets the physical transmit output current. pull?down this pin with a 6.49k (1%) resistor to ground. 8 agnd gnd analog ground. 9 vdd_a3.3 p 3.3v analog vdd input power supply (must be well decoupled). 10 rxm2 i/o port 2 physical receive (mdi) or transmit (mdix) signal (? differential). 11 rxp2 i/o port 2 physical receive (mdi) or transmit (mdix) signal (+ differential). 12 agnd gnd analog ground. 13 txm2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (? differential). 14 txp2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (+ differential). 15 fxsd2 i fiber signal detect input for port 2 in 100 base ? fx fiber mode. when in copper mode, this input is unused and should be pulled to gnd. note: this functionality is available only on the ksz8462fhl. 16 vdd_col p this pin is used as a second input for the low - voltage analog power. its source should have appropriate filtering with a ferrite bead and capacitors. 17 pwrdn ipu full?chip power?down : active low (low = p ower down; high or floating = n ormal operation). while this pin is asserted low, a ll i/o pins will be tri ? state d. all registers will be set to their default state. while this pin is asserted, power consumption will be minimal. when the pin is de?asserted, power consumption will climb to nominal and the device will be in the same state as having been reset by the reset pin (rstn, pin 63). 18 x1 i 25 mhz c rystal or o s cillator c lock c onnection : pins (x1, x2) connect to a crystal or frequency oscillator source. if an oscillator is used, x1 connects to a vdd_io voltage tolerant oscillator and x2 is a no connect. this clock requirement is 50ppm. 19 x2 o legend: p = power supply gnd = ground i/o = bi?directional i = input o = output. ipd = input with internal pull?down (58k 30%). ipu = input with internal pull?up (58k 30%). opd = output with internal pull?down (58k 30%). opu = output with internal pull?up (58k 30%). ipu/o = input with internal pull?up (58k 30%) during power?up/reset; output pin otherwise. ipd/o = input with internal pull?down (58k 30%) during power?up/reset; output pin otherwise. i/o (pd) = bi?directional input/output with intern al pull?down (58k 30%). i/o (pu) = bi?directional input/output with internal pull?up (58k 30%). micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 25 revision 1.0 pin description (continued) pin number pin name type pin function 20 dgnd gnd digital ground 21 vdd_io p 3.3v, 2.5v or 1.8v digital vdd input power pin for io logic and the internal low - voltage regulator. 22 sd15/be3 i/o (pd) shared data bus bit[15] or be3 : this is data bit (d15) access when cmd = ?0?. this is byte enable 3 (be3, 4th byte enable and active high) at double?wor d boundary access in 16?bit bus mode when cmd = 1. this pin must be tied to gnd in 8?bit bus mode. 23 sd14/be2 i/o (pd) shared data bus bit [ 14] or be2 : this is data bit (d14) access when cmd = ?0?. this is byte enable 2 (be2, 3rd byte enable and active high) at double?word boundary access in 16?bit bus mode when cmd = 1. this pin must be tied to gnd in 8?bit bus mode. 24 sd13/be1 i/o (pd) shared data bus bit [ 13] or be1 : this is data bit (d13) access when cmd = ?0?. this is byte enable 1 (be1, 2nd byte enable and active high) at double?word boundary access in 16?bit bus mode when cmd = 1. this pin must be tied to gnd in 8?bit bus mode. 25 sd12/be0 i/o (pd) shared data bus bit [ 12] or be0 : this is data bit (d12) access when cmd = ?0?. this is byte enab le 0 (be0, 1st byte enable and active high) at double?word boundary access in 16?bit bus mode when cmd = 1. this pin must be tied to gnd in 8?bit bus mode. 26 sd11 i/o (pd) shared data bus bit [ 11] : this is data bit (d11) access when cmd = ?0?. don?t care when cmd = 1. this pin must be tied to gnd in 8?bit bus mode. 27 sd10/a10 i/o (pd) shared data bus bit [ 10] : this is data bit (d10) access when cmd = 0. in 8?bit bus mode, this pin must be tied to gnd. in 16?bit bus mode, this is address a10 acces s when cmd = ?1?. 28 sd9/a9 i/o (pd) shared data bus bit[ 9] or a9 : this is data bit (d9) access when cmd = 0. in 8?bit bus mode, this pin must be tied to gnd. in 16?bit bus mode, this is address a9 access when cmd = ?1?. 29 dgnd gnd digital ground . 30 vdd_io p 3.3v, 2.5v or 1.8v digital vdd input power pin for io logic and the internal low - voltage regulator . 31 sd8/a8 ipu/o shared data bus bit [ 8] or a8 : this is data bit (d8) access when cmd = 0. in 8?bit bus mode, this pin must be tied to gnd. in 16?bit bus mode, this is address a8 access when cmd = ?1?. 32 sd7/a7 ipd/o shared data bus bit [ 7] or a7 : this is data bit (d7) access when cmd = 0. in 8?bit bus mode, this is address a7 (1 st write) or don?t care (2 nd write) access when cmd = 1. in 16?bit bus mode, this is address a7 access when cmd = 1. 33 sd6/a6 ipu/o shared data bus b it [ 6] or a6: this is data bit (d6) access when cmd = 0. in 8?bit bus mode, this is address a6 (1 st write) or don?t care (2 nd wr ite) access when cmd = 1. in 16?bit bus mode, this is address a6 access when cmd = 1. 34 sd5/a5 ipu/o shared data bus bit [ 5] or a5 : this is data bit (d5) access when cmd = 0. in 8?bit bus mode, this is address a5 (1 st write) or don?t care (2 nd write) access when cmd = 1. in 16?bit bus mode, this is address a5 access when cmd = 1. 35 sd4/a4 ipd/o shared data bus bit [ 4] or a4 : this is data bit (d4) access when cmd = 0. in 8?bit bus mode, this is address a4 (1 st write) or don?t care (2 nd wr ite) access when cmd = 1. in 16?bit bus mode, this is address a4 access when cmd = 1. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 26 revision 1.0 pin description (continued) pin number pin name type pin function 36 sd3/a3 i/o (pd) shared data bus bit [ 3] or a3 : this is data bit (d3) access when cmd = ?0?. in 8?bit bus mode, this is address a3 (1 st write) or don?t care (2 nd write) access when cmd = 1. in 16?bit bus mode, this is address a3 access when cmd = 1. 37 sd2/a2 i/o (pd) shared data bus bit [ 2] or a2 : this is data bit (d2) access when cmd = ?0?. in 8?bit bus mode, this is address a2 (1 st write) or a10 (2 nd write) access when cmd = ?1?. in 16?bit bus mode, this is address a2 access when cmd = 1. 38 sd1/a1/a9 i/o (pd) shared data bus bit [ 1] or a1 or a9 : this is data bit (d1) access when cmd = ?0?. in 8?bit bus mode, this is address a1 (1 st write) or a9 (2 nd write) access when cmd = 1. in 16?bit bus mode, this is dont care when cmd = 1. 39 dgnd gnd digital ground. 40 vdd_l p this pin can be used in two ways; as the pin to input the low volta ge to the device if the internal low - voltage regulator is not used, or as the low - voltage output if the internal low - voltage regulator is used. 41 sd0/a0/a8 ipu/o shared data bus bit [ 0] or a0 or a8 : this is data bit (d0) access when cmd = ?0?. in 8?bit bus mode, this is address a0 (1 st write) or a8 (2 nd write) access when cmd = 1. in 16?bit bus mode, this is dont care when cmd = 1. 42 cmd ipd command type : this command input decides the sd[15:0] shared data bus access information. when command in put is low, the access of shared data bus is for data access either sd[15:0] ?> data[15:0] in 16?bit bus mode or sd[7:0] ?> data[7:0] in 8?bit bus mode. when command input is high, in 16?bit bus mode: the access of shared data bus is for address a[10:2] a ccess at shared data bus sd[10:2] and sd[1:0] is ?don?t care". byte enable be[3:0] at sd[15:12] and the sd[11] is dont care. in 8?bit bus mode: it is for address a[7:0] during 1 st write access at shared data bus sd[7:0] or a[10:8] during 2 nd write acces s at shared data bus sd[2:0] (sd[7:3] is don?t care). 43 intrn opu interrupt output : this is an active low signal going to the host cpu to indicate an interrupt status bit is set. this pin needs an external 4.7k pull?up resistor. 44 rdn ipu read strobe : this signal is an active low signal used as the a synchronous read strobe during read acces s cycles by the host processor. it is recommended that it be pulled up with a 4.7k ? ohm resistor. 45 wrn ipu write strobe: this is an a synchronous write strobe sig nal used during write cycles from the external h ost processor. it is a low active signal. 46 pme/eeprom ipd/o power management event: this output signal indicates that a wake -on- lan event has been detected. the ksz8462 is requesting the system to wake up from low power mode. its assertion polarity is programmable with the default polarity to be active low. config mode: (eeprom) : at the end of the power up / reset period, this pin is sampled and the pull ? up/pull ? down value is latched. the va lue latched will indicate if a s erial eeprom is present or not. see the ? strapping options? section for detail s . 47 csn ipu chip select: this signal is the chip - select signal that is used by the ex ternal host processor for accesses to the device. it is an active low si gnal. 48 gpio0 i/o(pu) general purpose input/output [0] : this pin can be used as an input or output pin for use by the ieee 1588 event trigger or timestamp capture units. it will be synchronized to the internal ieee 1588 clock. the h ost p rocessor can also directly drive or read this gpio pin. 49 gpio1 i/o(pu) general purpose input/output [1] : re fer to gpio0 pin 48 description . micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 27 revision 1.0 pin description (continued) pin number pin name type pin function 50 dgnd gnd digital ground. 51 vdd_l p this pin can be used in two ways; as the pin to input the low voltage to the device if the internal low - voltage regulator is not used, or as the low - voltage output if the internal low - voltage regulator is used. 52 gpio2 i/o(pu) this pin is gpio2 (refer to gpio0 pin 48 description). 53 gpio3/eesk i/o(pd) default function: eeprom serial clock output : a serial output clock is used to load configuration data into the ksz8462 from the external eeprom when it is present. alternate function: general purpose input/output [3] : this pin can be used as an input or output pin for use by the ieee 1588 event trigger or timestamp capture units. it will be synchronized to the internal ieee 1588 clock. the host processor can also directly drive or read this gpio pin. function of this pin is controlled by bit[5] in iomxsel register. 54 gpio4/eedio i/o(pd) default function: eeprom data input/output : serial data input/output is from/to external eeprom when it is present. alternate function: general purpose input/output [4] : this pin can be used as an input or output pin for use by the ieee 1588 event trigger or timestamp capture units. it will be synchronized to the internal ieee 1588 clock . the host p rocessor can also directly drive or read this gpio pin. function of this pin is con trolled by b it[2] in iomxsel register. 55 gpio5/eecs i/o(pd) default function: eeprom chip select output : this signal is used to select an external eeprom device when it is present. alternate function: general purpose input/output [5] : this pin can be us ed as an input or output pin for use by the ieee 1588 event trigger or timestamp capture units. it will be synchronized to the internal ieee 1588 cloc k. the host p rocessor can also directly drive or read this gpio pin. function of this pin is controlled b y bit[1] in iomxsel register. 56 vdd_io p 3.3v, 2.5v or 1.8v digital vdd input power pin for io logic and the internal low - v oltage regulator . 57 dgnd gnd digital ground . 58 gpio6 i/o(pu) general purpose input/output [6] : r e fer to gpio0 pin 48 description . micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 28 revision 1.0 pin description (continued) pin number pin name type pin function 59 p1led1 ipu /o programmable led outputs to indicate port 1 and port 2 activity/s tatus: the led is on (active) when output is low; the led is off (inactive) when output is high. the port 1 led pins outputs are determined by the table below if reg. 0x06c ? 0x06d, bits [ 14:12] are set to ?000?. otherwise, the port 1 led pins are controlled via the processor by setting reg. 0x06c ? 0x06d, bits[ 14:12] to a non- zero value. the port 2 led pins outputs are determined by the table below if reg. 0x084 ? 0x085, bits[ 14:12] are set to ?000?. otherwise, the port 2 led pins are controlled via the processor by setting reg. 0x084 ? 0x085, bits[ 14:12] to a non - zero value. automatic port 1 and port 2 indicators are defined as follows: two bits[ 9:8] in sgcr7 control register 00 (default) 01 10 11 p1led1/p2led1 speed act duplex duplex p1led0/p2led0 link/act link link/act link link = led on act = led blink link/act = led on/blink speed = led on (100bt) led off (10bt) duplex = led on (full duplex) led off (half duplex) config mode: (p1led1): at the end of the power up / reset period, this pin is sampled and the pull - up/pull - down va lue is latched. it must be at a logic high level at this time. see the strapping options section for details. config mode: (p1led0/h816) : at the end of the power up / reset period, this pin is sampled and the pull?up/pull?down value is latched. the value latched will determine if 8?bit or 16?bit mode will be used for the host interface. see the strapping options section for details. config mode: (p2led0/lebe) : at the end of the power up / reset period, this pin is sampled and the pull?up/pull?down value is latched. the value latched will determine if ?little endian? or ?big endian? mode will be used for the host interface. see the strapping options section for details. 60 p1led0/h816 ipu /o 61 p2led1 o 62 p2led0 / lebe ipu /o 63 rstn ipu reset : hardware reset pin. (active low ) this reset input is require d to be low for a minimum of 10 ms after supply voltages vdd_io and 3.3v are stable. 64 fxsd1 i fiber signal detect : fiber signal detect input for port 1 in 100 base? fx fiber mode. when in copper mode, this input is unused and should be pulled to gnd. note : this functionality is available only on the ksz8462fhl device. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 29 revision 1.0 strapping options pin number pin name type pin function during power - up / reset 46 pme/ eeprom ipd /o eeprom select pull?up = eeprom present , nc or p ull? down (default ) = eeprom not present. this pin value is latched into register ccr, bit [9] at the end of the power -on- reset time. 59 p1led1 ipu/o reserved nc or pull - up (default) = normal operation , pull - down = reserved 60 p1led0/ h816 ipu/o 8 or 16?bit bus mode select nc or p ull? up (default ) = 16?bit bus mode , p ull?down = 8?bit bus mode . this pin value is also latched int o register cc r, bit [7:6] at the end of the power -on-r eset time. 62 p2led0/ lebe ipu/o endian mode select for 8/16 - bit host interface nc or p ull?up (default) = little endian , p ull?down = big endian . this pin value is latched into register ccr, bit [10] at the end of the power -on-r eset time. note s : ipu/o = input with internal pull?up (58k 30%) during power?up/reset; output pin otherwise. ipd/o = input with internal pull?down (58k 30%) during power? up/reset; output pin otherwise. all strap?in pins are latched during power?up or reset as well as re?strap?in when hardware/software power - down and hardware reset . micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 30 revision 1.0 functional description the ksz8462hl/fhl is a highly - integrated networking device that incorporates a layer?2 switch, two 10bt/100bt physical layer transceivers (phys) and associated mac units, and a bus interface unit (biu) with one general 8/16?bit host interface, and key ieee 1588 precision time protocol (ptp) features. the ksz8462hl/fhl operates in a managed mode. in managed mode, a host processor can access and control all phy, switch, mac, and ieee 1588 related registers within the device via the host interface. physical signal transmission and reception are enhanced through the use of analog circuits in the phy that make the design more efficient and allow for low power consumpt ion. both power management and energy - e fficient e thernet (eee) are designed to save more power while device is i n idle state. wake - on- lan is implemented to allo w the ksz8462 to monitor the network for packets intended to wake up the system which is upstream from the ksz8462. the ksz8462hl/fhl is fully compliant to ieee802.3u standards. direction terminology readers should note that two different terminologies are used in this datasheet to describe the direction of data flow . in the standard terminology that is used for all micrel switches, directions are described from the point of view of the switch core: ?transmit? indicates data flow out of the ksz8462 on any o f the three ports , while ?receive? indicates data flow into the ksz8462 . this terminology is used for the mib counters. when referencing the qmu block, which is located on port 3 between the internal mac and the external 8/16 - bit host interface, directions are revered ? they are described from the point of view of the external host processor. thus, ?transmit? indicates data flow from the host into port 3 of the ksz8462, while ?receive? indicates data flow out of the ksz8462 on port 3. since both terminologi es are used for port 3, it is important to note whether or not a particular section refers to the qmu. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 31 revision 1.0 physical ( phy ) block 100base ? tx transmit the 100base?tx transmit function performs parallel?to?serial conversion, 4b/5b coding, scrambling, nrz?to?nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel?to?serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz?to?nrzi format, and then transmitted in mlt3 current output. an external 6.49k w (1%) resistor for the 1:1 transformer ratio sets the output current. the output signal has a typical rise/fall time of 4ns and complies with the ansi tp?pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave?shaped 10base?t output driver is also incorporated into the 100base?tx driver. 100base ? tx receive the 100bas e?tx receiver function performs adaptive equalization, dc restoration, mlt3?to?nrzi conversion, data and clock recovery, nrzi?to?nrz conversion, de?scrambling, 4b/5b decoding, and serial?to?parallel conversion. the receiving side starts with the equalizat ion filter to compensate for inter?symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to optimize performance. in this desi gn, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. this is an ongoing process and self?adjusts against environmental chan ges such as temperature variations. next, the equalized signal goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential da ta conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de?scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to an mii format and provided as the input data to the mac. scrambler/de ?s crambler (100base ?tx o nly) the purpose of the sc rambler is to spread the power spectrum of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11?bit wide linear f eedback shift register (lfsr). after t he scrambler generates a 2047?bi t non?repetitive sequence, the receiver de?scrambles the incoming data stream using the same sequence as at the transmitter. pll clock synthesizer (recovery) the internal pll clock synthesizer generates 125mhz, 62.5mhz and 31.25mhz clocks for the ksz8462 system timing. these internal clocks are generated from an external 25mhz crystal or oscillator. refer to the device clocks section for more detailed information. 100base ? fx operation fiber mode is available only on the ksz8462fhl device. 100base?f x operation is similar to 100base?tx operation except that the scrambler/de?scrambler and mlt3 encoder/decoder are bypassed on transmission and reception. in this fiber mode, the auto ? negotiation feature is bypassed and auto mdi/mdix is disabled since ther e is no standard that supports fiber auto ? negotiation and auto mdi/mdix mode. the fiber port must be forced to either full?duplex or half?duplex mode. all ksz8462 devices are in copper mode (10 base - t / 100 base - tx) when reset or powered on. fiber mode is e nabled by clearing bits[ 7:6] in the cfgr register (0x0d8 - 0x0d9). each port is individually configurable. bit [13] in the dsp_cntrl_6 register (0x734 - 0x735) should also be cleared if either (or both) ports are set to fiber mode. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 32 revision 1.0 100base ? fx signal detection in 100base ? fx operation, the fiber signal detect input s ( fxsd ) are usually connected to the signal detect (sd ) output pin of the fiber transceiver . when fxsd is low , no fiber signal is detected and a far ? end fault (fef) is generated. when fxsd is high , the fiber signal is detected. to ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver sd output voltage swing to match the fxsd pin?s input voltage threshold . alternatively, the user may choose not to implemen t the fef feature. in this case, the fxsd input pin is tied high to force 100base ? fx mode. in copper mode, and on the ksz8462hl, the fxsd pins are unused and should be pulled low. 100base ? fx far ? end fault a far?end f ault (fef) occurs when the signal detect ion is logically false on the receive side of the fiber transceiver. the ksz8462fhli detects a n fef when its fxsd input is below the f iber s ignal detect t hreshold . when an fef is detected, the ksz8462fhli signals its fiber link partner that a fef has occur red by sending 84 1?s followed by a zero in the idle period between frames. by default, fef is enabled. fef can be disabled through register setting in p1cr4[12] and p2cr4[12]. 10base ? t transmit the 10base?t driver is incorporated with the 100base?tx driv er to allow for transmission using the same magnets. they are internally wave?shaped and pre?emphasized into outputs with typical 2.3v amplitude. the harmonic contents are at least 27db below the fundamental frequency when driven by an all?ones manchester? encoded signal. 10base ? t receive on the receive side, input buffers and level detecting squelch circuits are employed. a differential input receiver circuit a nd a phase?locked loop (pll) perform the decoding function. the manchester?encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulse widths to prevent noise at the rxp1 or rxm1 input from falsely triggering the decoder. when the input exceeds the squelch limit, th e pll locks onto the incoming signal and the ksz8462 decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. mdi/mdi ? x auto crossover to eliminate the need for crossover cables between similar devices, the ksz8462 supports hp?auto mdi/mdi?x and ieee 802.3u standard mdi/mdi?x auto crossover. hp?auto mdi/mdi?x is the default. the auto?sense function detects remote transmit and receive pair s and correctly assigns the transmit and receive pairs for the ksz8462 device. this feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. the auto?crossover feature can be disabled through the port control registers. the ieee 802.3u standard mdi and mdi?x definitions are noted in table 1 : table 1 . mdi/mdi - x pin definitions mdi mdi?x rj45 pins signals rj45 pins signals 1 td+ 1 rd+ 2 td? 2 rd? 3 rd+ 3 td+ 6 rd? 6 td? micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 3 3 revision 1.0 straight cable a straight cable connects an mdi device to an mdi?x device or an mdi?x device to an mdi device. figure 1 shows a typical straight cable connection between a network interface card (nic) and a switch, or hub (mdi?x). figure 1 . typical straight cable connection crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi?x device to another mdi?x device. figure 2 shows a typical crossover cable connection between two chips or hubs (two mdi?x devices). figure 2 . typical crossover cable connection micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 34 revision 1.0 auto?negotiation the ksz84 62 conforms to the auto ? negotiation protocol as described by ieee 802.3 . it allow s each port to operate at either 10 base ?t or 100 base ?tx. auto? negotiation allows unshielded twisted pair (utp) link partners to select the best common mode of operation. in auto ? negotiation , the link partners advertise capabilities across the link to each other and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. auto - negotiation is also used to negotiate support for energy efficient ethernet (eee). auto - negotiation is supported only on the copper ports and not the fiber ports. the following list shows the speed and duplex ope rat ion mode from highest to lowest: x highest: 100 base ? tx, full ? duplex x high: 100 base ? tx, half?duplex x low: 10 base ? t, full?duplex x lowest: 10 base ? t, half?duplex if auto ? negotiation is not supported or the link partner to the ksz8462 is forced to bypass auto ? ne gotiation , the mode is set by observing the signal at the receiver. this is known as parallel mode because while the transmitter is sending auto ? negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. the link s etup is shown in figure 3 . figure 3 . auto negotiation and parallel operation micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 35 revision 1.0 linkmd ? cable diagnostics the ksz8462 linkmd ? uses time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi and mdi?x pairs an d then analyzes the shape of the reflected signal. timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of 2m. internal circuitry displays the tdr information in a user?readable digital format in register p1scslmd[8:0] or p2scslmd[8:0]. note : c able diagnostics are only valid for copper connections . f iber?optic operation is not supported. access linkmd is initiated by accessing register p1scslmd (0x07c) or p2scslmd (0x094), the ph y special control/status & linkmd register. usage before initiating linkmd, the value 0x8008 must be written to the ana_cntrl_3 register (0x74c ? 0x74d). this needs to be done once (after power - on reset) , but does not need to be repeated for each initiatio n of linkmd. auto - mdix must also be disabled before using linkmd. to disable auto - mdix, write a ?1? to p1cr4[10] or p2cr4[10] to enable manual control over the pair used to transmit the linkmd pulse. the self - clearing cable diagnostic test enable bit, p1sc slmd[12] or p2scslmd[12], is set to ?1? to start the test on this pair. when bit p1scslmd[12] or p2scslmd[12] returns to ?0?, the test is completed. the test result is returned in bits p1scslmd[14:13] or p2scslmd[14:13] and the distance is returned in bits p1scslmd[8:0] or p2scslmd[8:0]. the cable diagnostic test results are as follows: 00 = valid test, normal condition 01 = valid test, open circuit in cable 10 = valid test, short circuit in cable 11 = invalid test, linkmd failed if p1scslmd[ 14:13] or p2scslmd[14:13] is ?11?, this indicates an invalid test, and it occurs when the ksz8462 is unable to shut down the link partner. in this instance, the test is not run, as it is not possible for the ksz8462 to determine if the detected signal is a reflection of the signal generated or a signal from another source. cable distance can be approximated by the following formula: p1scslmd[8:0] x 0.4m for port 1 cable distance p2scslmd[8:0] x 0.4m for port 2 cable distance this constant (0.4m) may be cal ibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. on ?c hip termination resistors the ksz8462 reduces board cost and simplifies board layout by using on?chip termination resistors for rx/tx differential pairs , eliminating the need for external termination resistors in copper mode . the on- chip termination and internal biasing will provide significant power savings when compared with using external biasing and termination re sistors. loopback support the ksz8462 provi des two loopback modes . o ne is n ear? end (remote) l oopback to support remote diagnosing of failures on line side, and the other is far?end loopback to support local diagnosing of failures through all blocks of the device. in loopback mode, the speed of the phy port will be set to 100base?tx full?duplex mode. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 36 revision 1.0 far ? end loopback far? end loopback is conducted between the ksz8462 ?s two phy ports. th e loopback path starts at the ?o riginating? phy port?s receive inputs (r xp/rxm), wraps around at the ?loopback? phy port?s physical media dependent/physical media attachment ( pmd/pma ), and ends at the ?o riginating? phy port?s transmit outputs (txp/txm). bit[8] of registers p1cr4 and p2cr4 is used to enable far?end loopback for port s 1 and 2, respectively. as an alternative, bit[14] of registers p1mbcr and p2mbcr can be used to enable far?end loopback. the port 2 f ar? end l oopback path is illustrated in the figure 4 . near ? end (remote) loopback near?end (remote) loopback is conducted at either the port 1 phy or port 2 phy . the loopback path starts at the phy port?s receive inputs (rxpx/rxmx), wraps around at the same phy port?s pmd/pma (physical media dependent/physical media attachment) block , and ends at the same phy port?s transmit outputs (txpx/txmx). bit[1] of registers p1phyctrl and p2phyctrl is used to enable n ear? end l oopback for port s 1 and 2, res pectively. as an alternative, bit[9] of registers p1scslmd and p2scslmd can be used to enable n ear? end loopback. the n ear? end l oopback paths for port 1 and port 2 are illustrated in figure 4 . figure 4 . near - end and far - end loopback micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 37 revision 1.0 media access controller (mac) block mac operation the ksz8462 strictly abides by ieee 802.3 standards to maximize compa tibility. additionally, there is an added mac filtering function to filter u nicast packets. the mac filtering function is useful in applications such as voip where restricting certain packets reduces congestion and thus improves performance. address lookup the internal dynamic mac address lookup table stores mac addresses and their associated information. it contains a 1k entry u nicast address learning table plus switching information. the ksz8462 is guaranteed to learn 1k addresses and distinguishes itself from hash?based lookup tables, which , depending on the operating environment and probabilities, may not guarantee the absolute number of addresses they can learn. learning the internal lookup engine updates the dynamic mac address table with a new entry i f the following conditions are met: ? the received packet's source address (sa) does not exist in the lookup table. ? the received packet has no receiving errors , and the packet size is of legal length. the lookup engine inserts the qualified sa into the table, along with the port number and time stamp. if the table is full, t he oldest entry of the table is deleted to make room for the new entry. migration the internal lookup engine also monitors whether a station has moved. if a station has moved, it updates the dynamic table accordingly. migration happens when the following conditions are met: ? the received packet's sa is in the table but the associated source port information is different. ? the received packet has no receiving errors , and the packet size is of legal length. the lookup engine updates the existing record in the table with the new source port information. aging the lookup engine updates the time stamp information of a record whenever the co rresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the lookup engine removes the record from the table. the lookup engine constantly performs the aging process and continuously removes agin g records. the aging period is about 300 seconds , 75 seconds. this feature can be enabled or disabled through global r egister sgcr1[10]. forwarding the ksz8462 forwards packets using the algorithm that is depicted in the following flowcharts. figure 5 shows stage one of the forwarding algorithm where the search engine looks up the vlan id, static table, and dynamic table for the destination address, an d comes up with ?port to forward 1? (ptf1). ptf1 is then further modified by spanning tree, igmp snooping, port mirroring, and port vlan processes to come up with ?port to forward 2? (ptf2), as shown in figure 6 . the packet is sent to ptf2. the ksz8462 will not forward the following packets: ? error packets: these include framing errors, frame check s equence (fcs) errors, alignment errors, and illegal size packet errors. ? ieee802.3x pause frames: ksz8462 intercepts these packets and performs full duplex flow control accordingly. ? "local" packets: based on destination address (da) lookup. if the destination port from the lookup table matches the port from whic h the packet originated, the packet is defined as "local." micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 38 revision 1.0 figure 5 . destination address lookup flow chart in stage one micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 39 revision 1.0 figure 6 . destination address resolution flow chart in stage two micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 40 revision 1.0 inter packet gap (ipg) if a frame is successfully transmitted, then the minimum 96?bit time for ipg is measured between two consecutive packets. if the current packet is experiencing collisions, the minimum 96?bit time for ipg is measured from carrier sense (crs ) to the next transmit packet. back ? off algorithm the ksz8462 implements the ieee standard 802.3 binary exponential back?off algorithm in half?duplex mode. after 16 collisions, the packet is dropped. late collision if a transmit packet experiences collisio ns after 512 bit times of the transmission, the packet is dropped. legal packet size the ksz8462 discards packets less than 64 bytes and can be programmed to accept packet sizes up to 1536 bytes in sgcr2[1]. the ksz8462 can also be programmed for special a pplications to accept packet sizes up to 2000 bytes in sgcr1[4]. flow control the ksz8462 supports standard 802.3x flow control frames in both transmit and receive directions . in the receive direction , if a pause control frame is received on any port , the ksz8462 will not transmit the next normal frame on that port until the timer, specified in the pause control frame, expires. if another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pau se frame. during this period (while it is flow controlled), only flow control packets from the ksz8462 are transmitted. in the transmit direction , the ksz8462 has intelligent and efficient ways to determine when to invoke flow control and send pause frames . the flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues . the ksz8462 issues a pause frame containing the maximum pause time defined in ieee standard 802.3x. on ce the resource is freed up, the ksz8462 sends out another flow control frame with zero pause time to turn off the flow control (turn on transmission to the port). a hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. o n port 3, a flow control handshake exists internally between the qmu and the port 3 mac . in the qmu, there are three programmable threshold levels for flow control in the rxq fifo: 1) low water mark register fclwr (0x1b0), 2) high water mark register fchwr (0x1b2) , and 3) overrun water mark register fcowr (0x1b4). the qmu will send a pause frame internally to the mac when the rxq buffer fills with egress packets above the high water mark level (default 3.072 k b yte s available) , and a stop pause frame when the rxq buffer drops below the low water mark level (default 5.12 k b yte s available). the qmu will drop new packet s from the switch when the rxq buffer fills beyond the overrun water mark level (default 256 b yte s available). half ? duplex backpressure a half?duplex backpressure option (non?ieee 802.3 standard) is also provided. the activation and deactivation conditions are the same as in full?duplex mode. if backpressure is required, the ksz8462 sends preambles to defer the other s tations' transmission (carrier sense deference). to avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the ksz8462 discontinues the carrier sense and then raises it again quickly. this short silent time (no carr ier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. if the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead. if there are no additional packets to send, carrier sense type backpressure is reactivated again until chip resources free up. if a collision occurs, the binary exponential back?off algorithm is skipped and carrier sense is genera ted immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet reception. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 41 revision 1.0 to ensure no packet loss in 10base?t or 100base?tx half?duplex mode, the user must enable the following bits: ? aggressive back off ( bit[8] in sgcr1) ? no excessive collision drop (bit[3] in sgcr2) ? back pressure flow control enable (bit[11] in p1cr2/p2cr2) note : these bits are not set in default, since this is not the ieee standard. broadcast storm protection the ksz8462 has an intelligent option to protect the switch system from receiving too many broadcast packets. as the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. the ksz8462 has the option to include ?multicast packets? for storm control. the broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis in p1cr1[7] and p2cr1[7]. the rate is based on a 67ms interval for 100bt and a 670ms interval for 10bt. at the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. the rate definition is descri bed in sgcr3[2:0][15:8]. the default setting is 0x63 (99 decimal). this is equal to a rate of 1%, calculated as follows: 148,800 frames/sec 67 ms/interval x 1% = 99 frames/interval (approx.) = 0x63 note: 148,800 frames/sec is based on 64 ? byte block of p ackets in 100base ? t with 12 bytes of ipg and 8 bytes of preamble between two packets. port individual mac a ddress and source port filtering the ksz8462 can provide individual mac addresses for port 1 and port 2. they can be set at registers 0x0b0h - 0x0b5h a nd 0x0b6 - 0x0bb. received packets can be filtered (dropped) if their source address matches the mac address of port 1 or port 2. this feature can be enabled by setting bits[ 11:10] in the p1cr1 or p2cr1 registers. one example of usage is that a packet will b e dropped after it completes a full round trip within a ring network. address filtering function the ksz8462 supports 11 different address filtering schemes as shown in table 2 . the ethernet destination address (da) field inside the packet is the first 6?byte field which uses to compare with either the host mac address registers (0x110 ? 0x115) or the mac address hash table registers (0x1a0 ? 0x1a7) for address filtering operation. the first bit (bit[40]) of the destination address (da) in the ethernet packet decides whether this is a physical address if bit[40] is ?0? or a multicast address if bit[40] is ?1?. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 42 revision 1.0 table 2 . mac address filtering scheme item address filtering mode receive control register (0x174 ? 0x175): rxcr1 description rx all (bit [4]) rx inverse (bit [1]) rx physical address (bit [11]) rx multicast address (bit [8]) 1 perfect 0 0 1 1 all rx frames are passed only if the da exactly matches the mac address in marl, marm and marh registers. 2 inverse perfect 0 1 1 1 all rx frames are passed if the da is not matching the mac address in marl, marm, and marh registers. 3 hash only 0 0 0 all rx frames with either multicast or physical destination address are filtering against the mac address hash table. 4 inverse hash only 0 1 0 0 all rx frames with either multicast or physical destination address are filtering not against the mac address hash table. all rx frames which are filtering out at item 3 (hash only) only are passed in this mode. 5 hash perfect (default) 0 0 1 0 all rx frames are passed with physical address (da) matching the mac address and to enable receive multicast frames that pass the hash table when multicast address is matching the mac address hash table. 6 inverse hash perfect 0 1 1 0 all rx frames which are filtering out at item 5 (hash perfect) only are passed in this mode. 7 promiscuous 1 1 0 0 all rx frames are passed without any conditions. 8 hash only with multicast address passed 1 0 0 0 all rx frames are passed with physical address (da) matching the mac address hash table and with multicast address without any conditions. 9 perfect with multicast address passed 1 0 1 1 all rx frames are passed with physical address (da) matching the mac address and with multicast address without any conditions. 10 hash only with physical address passed 1 0 1 0 all rx frames are passed with multicast address matching the mac address hash table and with physical address without any conditions. 11 perfect with physical address passed 1 0 0 1 all rx frames are passed with multicast address matching the mac address and with physical address without any conditions. notes: bit [ 0 ] (rx enable), bit [ 5 ] (rx unicast enable) and bit [ 6 ] (rx multicast enable) must set to 1 in rxcr1 register. the ksz8462 will discard frame with sa same as the mac a ddress if bit[0] is set in rxcr2 register . micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 43 revision 1.0 switch block switching engine the ksz8462 features a high?performance switching engine to move data to and from the macs packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces overall latency. the switching engine has a 32kbyte internal frame buffer . this resource is shared between all the ports. there are a total of 256 buffers available. each buffer is sized at 128 bytes. spanning tree support to support spanning tree, the host port is the designated port for the processor. the other ports ( port 1 and port 2) can be configured in one of the five spanning tree states via ?transmit enable?, ?receive enable? and ?learning disable? register settings in registers p1cr2 and p2cr2 for port s 1 and 2, respectively. ta ble 3 shows the port setting and software actions taken for each of the five spanning tree states. table 3 . spanning tree states disable state port setting software action the port should not forward or receive any packets. learning is disabled. xmit enable = ?0?, receive enable = ?0?, learning disable = ?1? the processor should not send any packets to the port. the switch may still send specific packets to the pro cessor (packets that match some entries in the static mac address table with ?overriding bit? set) and the processor should discard those packets. addr ess learning is disabled on the port in this state. blocking state only packets to the processor are forwarded. xmit enable = ?0?, receive enable = ?0?, earning disable = ?1? the processor should not send any packets to the port(s) in this state. the processor should program the static mac address table with the entries that it needs to receive (for example, bpdu packets). the ?overriding? bit should also be set so that the switch will forward those specific packets to the processor. address learning is disabled on the port in this state. listening stat e only packets to and from the processor are forwarded. learning is disabled. xmit enable = ?0?, receive enable = ?0?, learning disable = ?1? the processor should program the static mac address table with the entries that it needs to receive (for example, bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processo r may send packets to the port(s) in this state. address learning is disabled on the port in this state. learning state only packets to and from the processor are forwarded. learning is enabled. xmit enable = ?0?, receive enable = ?0?, learning disable = ?0? the processor s hould program the static mac address table with the entries that it needs to receive (for example, bpdu packets). the ?ove rriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state. address learning is enabled on the port in this state. forwarding state packets are forwarded and received normally. learning is enabled. xmit enable = ?1?, receive enable = ?1?, learning disable = ?0? the processor programs the static mac address table with the entries that it needs to receive (for example, bpdu packets). the ?overriding? bit is set so that the switch forwards those specific packets to the processor. the processor can send packets to the port(s) in this state. addres s learning is enabled on the port in this state. micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 44 revision 1.0 rapid spanning tree support there are three operational states assigned to each port for rstp (discarding, learning, and forwarding): ? discarding ports do not participate in the active topology and do not learn mac addresses. ? discarding state: the state includes three states of the disable, blocking and listening of stp. ? port setting: xmit enable = ?0?, receive enable = ?0?, learning disable = ?1?. discarding state software action: the host processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static table with ?overriding bit? set) and the processor should discard those packets. when the port?s l earning capability (learning disable = ?1?) is disabled, setting bits[ 10:9] in the sgcr8 register will rapidly flush the port related entries in the dynamic mac table and static mac table. the processor is connected to port 3 via the host interface. addres s learning is disabled on the port in this state. learning state ports in ?learning states? learn mac addresses, but do not forward user traffic. learning state: only packets to and from the processor are forwarded. learning is enabled. port setting for learning state: transmit enable = ?0?, receive enable = ?0?, learning disable = ? 0?. software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit sh ould be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state (see tail tagging mode section for details.) address learning is enabled on the port in this state. ports in forwarding states fully participate in both data forwarding and mac learning. forwarding state forwarding state: packets are forwarded and received norma lly. learning is enabled. port setting: transmit enable = ?1?, receive enable = ?1?, learning disable = ?0?. software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see ?tail tagging mode? section for details. address learning is enabled on the port in this state. rst p uses only one type of bpdu called rstp bpdus. they are similar to stp configuration bpdus with the exception of a type field set to ?version 2? for rstp and ?version 0? for stp, and a flag field carrying additional information. tail tagging mode tail t ag mode is only seen and used by the port 3 host interface, which should be connected to a processor. it is an effective way to retrieve the ingress port information for spanning tree protocol, igmp snooping, and other applications . b it s [ 1 : 0 ] in the one byt e tail tagging are used to indicate the source/destination port in port 3. b its [ 3 : 2 ] are used for priority setting of the ingress frame in port 3 . other bits are not used. the tail t ag feature is enabled by setting bit [8] in the sgcr8 register. figure 7 . tail tag frame format micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 45 revision 1.0 table 4 . tail tag rules ingress to port 3 (host ? > ksz8462 ) b it [1 : 0] destination port 00 normal (address look up) 01 port 1 10 port 2 11 port 1 and port 2 bit [3 : 2] frame priority 00 priority 0 01 priority 1 10 priority 2 11 priority 3 egress from port 3 (ksz8462 ? > host) b it [0] source port 0 port 1 1 port 2 igmp support for internet group management protocol (igmp) support in layer 2, the ksz8462 provides two components: ?igmp? snooping the ksz8462 traps igmp packets and forwards them only to the processor (host port). the igmp packets are identified as ip packets (either ethernet ip packets, or ieee 802.3 snap ip packets) with ip version = 0x4 and protoco l version number = 0x2. ?multicast address insertion? in the static mac table once the multicast address is programmed in the static mac address table , the multicast session is trimmed to the subscribed ports, instead of broadcasting to all ports. to enable igmp support, set bit[14] to ?1? in the sgcr2 register. also, tail tagging mode needs to be enabled, so that the processor knows which port the igmp packet was received on. this is achieved by setting bit[8] to ?1? in the sgcr8 register. ipv6 mld snooping the ksz8462 traps ipv6 multicast listener discovery (mld) packets and forwards them only to the processor (host port). mld snooping is controlled by sgcr2, bit[13] (mld snooping enable) and sgcr2 bit[12] (mld option). setting sgcr2 bit[13] causes the ksz8462 to trap packets that meet all of the fo llowing conditions: ? ipv6 multicast packets ? hop count limit = ?1? ? ipv6 next header = 3 r u 3 r u 3 z l w k k r s e \ k r s q h [ w k h d g h u 3 r u 3 ? , i 6 * & |